Timothy Normand Miller wrote:
It won't be long before we'll have to design a nanocontroller for OGD1
to manage VGA and DMA. I may be able to just go off and design one
myself, but I think that many of you would fancy observing and
participating in the design process, and with more brains on it, we'd
do a better job.
...
...
Ok, I've read your whole idea.. and I have a question regarding the
memory access:
- is the DMA "hw accelerated", so that this new core will set only
addresses for fragments and the transfer is done automatically, you only
do the calculation of sizes because of interrupted pci tranfers?
or
- this new controller will actually do the DMA, which now becomes a
PIO from the card's POV because it is actually run by a nanoprogram. In
this case, the access through the second memory as a control block seems
to be slow to me.
And one more: For what else will it be used? I understand the VGA
emulation (address mapping, maybe pixel resizing), DMA (either of
above), but the core seems to be more complex than a nano. Is that the
last/main controller, and the rest of OGD1 will be more like hw (fixed
function units) ?
It would be better to start with a list of things to be controlled by
it, than designing it first and then attaching other modules. If there
is already such a list, please drop the url here.
Daniel
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