...
// Cause branch
input [1:0] branch_condition;
input [31:0] branch_reg_val;
What is branch_reg_val?
(I think I understand now, but you might want to comment about it)
...
// Decide if we're going to do a branch
reg do_branch;
wire beqz = branch_reg_val == 0;
wire bneg = branch_reg_val[31];
ok, so if I understand correctly, branch_reg_val is r_ix,
which is tested for all the conditions?
...
// Store the PC address we just used (advancing it by one).
always @(posedge clock) pc <= next_pc + 1;
// If this is a subroutine call, we need to pass the return address
// down the pipeline
always @(posedge clock) return_address <= pc + 2;
This is the only thing I am confused about. Suppose we have an
unconditional branch. Then pc = current_addr, next_pc=branch_addr,
but return address would point to the instruction after the one after
this
one. Why isn't it pc+1? What happens to the instruction at
current_addr+1?
Besides that, it looks good.
nick
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