On 4/1/07, Raphaël Jacquot <[EMAIL PROTECTED]> wrote:
http://www.techarp.com/showarticle.aspx?artno=391
This is every chip designer's worst fear. With software and to a large extent, FPGAs, bugs can be corrected in the field. But with ASICs, you're screwed. IIRC, bugs in my first major ASIC cost my employer many tens of thousands of dollars for a respin. Fortunately, they had written the budget up front to assume this. -- Timothy Normand Miller http://www.cse.ohio-state.edu/~millerti Open Graphics Project _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
