Hi, Could someone give me a hand for creating a testbench to test the multiplier? The part I would need help with, would be a program that generate some input and the result value in hex based on the float25 software model. If it could generate random value and corner case that would be great.
Thanks André 2007/7/25, André Pouliot <[EMAIL PROTECTED]>: > > Hello, > > Here is the first version for the float25 multiplier. The float are > based on the IEEE-754 specification but with a reduce mantissa to fit > the hardware on the spartan3. It's still doesn't have a test bench, I > still need to learn how to do one in verilog and install a simulator. > But it do pass synthesis for a spartan3 the resource used are 1 > multiplier and 110 flip-flop and 47 LUT. The result post-synthesis are > what I expected for the logic. > > It's a 4 stage multiplier. The input aren't latched before beginning the > bit manipulation, a supposition is made that the previous module will > latch is output data. > > First stage is used for verification if the mantissa value is normalized > or not by testing the exponent. Also in that stage the sign bit is > calculated and the incoming signal are split in the different part that > composed them. > > Second stage are where the true calculation take place, addition of the > exponent and multiplication of the mantissa. > > Third stage is where depending on the result of the mantissa we > normalizes the result. Selection of what part of the mantissa to keep > and correction of the exponent field, since there is an offset in the > exponent to compensate for. > > Four stage the value are rounded to 0 or infinite, if the exponent fall > below 1 or is bigger than 254. > > The part that could be ameliorated is the 4 stage with the rounding. > There is no support for how to handle unnormalized number except by > rounding them to zero. The result of the multiplication can't produce > NaN or unnormalized number. > > André >
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