On 9/4/07, Patrick McNamara <[EMAIL PROTECTED]> wrote: > I wasn't suggesting shifts in architecture, that would definitely be > bad. More I was suggesting something along the lines of replication of > existing structures. For example, suppose in OGP we wanted 8 parallel > fragment pipeline but only had room in the FPGA for four. If they are > designed properly, we set up the control to support eight and then only > put four in the FPGA. When we go to ASIC we add in the other four as > duplicates of the originals. Obviously there is new logic that cannot > be tested in the FPGA, but it should be minimal compared to something > like going from a single pipeline to multiple.
I see what you're saying. Now, specifically with regard to the rendering engine, where it would be most useful, I have in mind an approach that may not allow replication. The idea is to have one pixel pipeline that processes two pixels together, rather than two pipelines that each process one pixel. This way, any logic that can be shared is shared. > I have been thinking about this as well. There are definitely > advantages to going this route. We have to be careful though. We > either need a nanocontroller capable of arbitrary scaling and bitblt or > we need the graphics pipeline available to assist. Once you start > talking about arbitrary scaling and stuff like that you get to the point > where the nanocontroller isn't so "nano" anymore. I was not thinking that the VGA would scale arbitrarily. Maybe integer scaling, but otherwise, we'd just center it on the screen and deal. There's absolutely no reason it has to be seamless. It just has to be adequate. -- Timothy Normand Miller http://www.cse.ohio-state.edu/~millerti Open Graphics Project _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
