Timothy Normand Miller wrote:
In order to implement a proof-of-concept, we would need to know a lot
about the logic cell and routing resources of common FPGAs, or at
least a toy FPGA architecture that we could scale up once we got the
basic principles down. So, for instance, I would want to be able to
specify to some helper code that I want to place this gate here and
that gate there, and route between them using the K-th best route.
Have you looked at VPR
(http://www.eecg.toronto.edu/~vaughn/vpr/vpr.html)? It models a toy
FPGA architecture and would give you a framework to start with. It's
not the best model for a modern FPGA as it lacks multipliers, RAMs,
carry chains, direct-drive wires, "bent" wires (like the V5 "diagonal"
routing), etc., but it's a start. It's also a pretty strong annealing
placer/maze router, so it would give you an interesting baseline to
compare your algorithm against in terms of speed/QoR/etc.
In other words, our near-term goal is to produce functional Free P&R
tools, not blaze trails in the cutting edge of VLSI. (We can do that
later.)
It might be difficult to get sufficiently detailed descriptions of the
routing architecture from FPGA companies to be able to do routing. Even
without reaching for the cutting edge of VLSI, functional free PAR may
be a big enough challenge in and of itself. :)
To that end, maybe it's easier to modify VPR to target a real
architecture than it is to create a whole new tool and new techniques
for placement and routing.
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