I'm sure many of you have seen this:
http://linux.slashdot.org/article.pl?sid=07/11/04/192214
The CPU is quite impressive. I thought it would perhaps be
interesting, if the original author doesn't mind, if we were to code
this up in Verilog. It could be a great educational tool to be able
to have schematics and Verilog side-by-side.
We wouldn't necessarily want to make the reference design
synthesizable for OGD1. For instance, he probably expects fixed
latency for accessing main memory, which would be impossible to
achieve in OGD1 with its graphics memory. To make it actually run in
OGD1 would require some modifications, which is okay, but to start
with, a direct "port" of this design, that is synthesizable in
_principle_, would be very interesting. (We'd mostly just simulate
it.)
Since all the problems have been worked out (i.e. no problems to
solve, no design work to be done), porting this to Verilog would be a
quick thing for an experienced chip designer. As such, it would be
more useful for those who are less experienced to try their hands at
it instead.
It was JHB or someone who he was quoting who suggested we make models
of 74-series in Verilog. We could start at that level. Which chips
are used here? I don't remember many of the 74-series chips, but
others do and can look at the diagrams. Let's just start posting the
snippets of Verilog code to the list for each of the chips and build
up from there.
I'm probably missing something, but here's a start on one of them.
module IC74138(
input en1,
input en2,
input nen3,
input [7:0] in,
input [2:0] select,
output out);
out = in[select] & en1 & en1 & ~nen3;
endmodule
module IC74377(
input e_bar,
input [7:0] in,
output reg [7:0] out,
input clock);
always @(posedge clock) begin
if (e_bar == 0) out <= in;
end
endmodule
--
Timothy Normand Miller
http://www.cse.ohio-state.edu/~millerti
Open Graphics Project
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