On 06/11/2007, Michael Meeuwisse <[EMAIL PROTECTED]> wrote: > Let me start off by saying that I still think you're all doing a > fantastic job, and that my comments where (and are) meant to be > constructive, not offensive. If it sounded otherwise, I apologise in > advance.[1]
Your questions have advanced the documentation. I have added most of the components to the components page - anything we are missing? Also we probably want to have some pictures of the pin layouts for the main chips. Any volunteers? It is basically a box wtih lines for pins and labels for the pins. I have used a table but it doesn't look too great. > >> and we (the community) still don't know how to start writing verilog > >> for something like a controller for the FPGA<->CPLD bus. With a start of some simple verilog examples this should help more people to learn. Please Keep asking and documenting. I have been meaning to go through the schematics but not enough time at present. timothy wrote > > Next, the important information you need IS available online. It's > > just encoded in an unfamiliar way. The best way for the community to > > help themselves would be for some of its members to become familiar > > with reading schematics. snip > > That's exactly why I started firing off a dozen questions about the > bridge. excellent. I also have created a blank page on the wiki - we might detail the connections to each fpga. link via: http://wiki.opengraphics.org/tiki-index.php?page=OGD1+components+guide > > I believe this would fit nicely on the VGARoadmap page, I'll add a > written out version to it this weekend hopefully (unless somebody > beats me to it). > excellent. Also some details may belong on the lattice fpg page - we might want a page to explain what pin goes where. http://wiki.opengraphics.org/tiki-index.php?page=OGD1_U12 > > > > It sounds like you're talking about the bridge. This is a bus between > > the small FPGA and the large one. > > > > The 32 bits are for address and data. The control lines indicate > > things about what is being carried on the data lines. The data issnip So we'll end up with a more-or-less PCI > controller on the FPGA, which has C/BE[3:0] and AD[0:31] lines. I > also figure we end up with IRDY/TRDY/FRAME and an interrupt line. > DEVSEL, IDSEL and STOP can probably be left out, as well as PERR and > SERR, although some sort of recovery must be available. this could be also added to the glossary http://wiki.opengraphics.org/tiki-index.php?page=Glossary Under PCI - though eventually we will probably have a separate page explaining about PCI. > snip the vga roadmap is a good place. http://wiki.opengraphics.org/tiki-index.php?page=VGARoadmap we have hidden it by naming it draft documentaton under the docs page to give some space for it to grow - as soon as it is good enough, we should fix the link.. Perhaps we should do it after your edits. > Mike > www.wacco.mveas.com - Project VGA > thanks jb _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
