Slower logic would use an SR flipflop in place of the first inverter/buffer. That might or might not be a good idea for ECL -- not sure.
You need to run the output through a D flipflop to divide by two (for perfect 50% duty cycle) and then convert to what ever logic levels you needed. If one buffer stage doesn't give a fast enough clock rise time, you would need to use additional ones in series.
The bottom R (100 ohm) & C could be replaced by 1.6 volts bias supply (for LVPECL -- which must sink not source current) which would be better.
I used NMOS transistors for the two VCCSes, but something else could be used. IIUC, the VCCSes are going to determine the frequency ratio since as the current is reduced, the parasitic capacitance is more and more significant and the oscillator capacitor isn't very large even with the 50 ohm resistors.
RF circuits are not my thing, so I don't know what else would be needed for a practical circuit. I presume that the voltage IN would need a series choke and collector catcher diodes (Schottky) might be a good idea on the output of the first inverter buffer (but then we have another bias voltage). And, the outputs need to be terminated -- supposed to be 50 ohms to 1.6v (LVPECL).
This has an offset where the voltage IN starts at 1.6 volts, if a bias supply is used, so a level shifter op amp might be a good idea for the voltage in -- the loop filter needs a voltage follower any way.
-- JRT
VCO.pdf
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