Below are the top-level modules for the two chips. Later, for
simulation, when we've decided on the bridge specifics, we'll build a
simulation top-level that stitches them together.
module XP10_top_level(
// PCI bus (missing some master signals)
input pci_clk,
input pci_rst_,
output pci_int, // open collector
inout [31:0] ad,
inout par,
inout [3:0] cbe_,
inout frame_,
inout idsel,
inout irdy_,
inout devsel_,
inout perr_,
inout stop_,
inout trdy_,
// Bridge
inout [31:0] bridge_ad,
output [3:0] bridge_bytes,
inout [11:0] bridge_other, // define these soon
output bridge_clock,
// DDC interface
inout top_ddc_clk,
inout top_ddc_data,
input top_hotplug,
inout bot_ddc_clk,
inout bot_ddc_data,
input bot_hotplug,
inout top_i2c_sda,
inout top_i2c_scl,
inout bot_i2c_sda,
inout bot_i2c_scl,
output video_reset,
// VGA BIOS PROM Interface
output bios_si,
input bios_so,
output bios_ce_,
output bios_sck,
// Xilinx FPGA PROM Interface
output config_si,
input config_so,
output config_ce_,
output config_sck,
// Power-down control for DACs
output bot_dac_pwr_off,
output top_dac_pwr_off,
// Main FPGA Control
output xilinx_m0,
output xilinx_m1,
output xilinx_m2,
output xilinx_cclk,
output xilinx_din,
input xilinx_done,
output xilinx_programn,
input xilinx_initn,
// Oscillators and such
// ...
// Test points
// ...
);
endmodule
Module Spartan3_top_level(
// Clock inputs
// ...
// Bridge Interface
inout [31:0] bridge_ad,
input [3:0] bridge_bytes,
inout [11:0] bridge_other, // define these soon
input bridge_clock,
// I/O to RAM chip A
output Aras_out,
output Acas_out,
output Awr_out,
output [3:0] Adm_out,
output [12:0] Aaddr_out,
output [1:0] Abank_out,
inout [31:0] Adq,
inout [3:0] Adqs,
output [1:0] Aram_clkp,
output [1:0] Aram_clkn,
// I/O to RAM chip B
output Bras_out,
output Bcas_out,
output Bwr_out,
output [3:0] Bdm_out,
output [12:0] Baddr_out,
output [1:0] Bbank_out,
inout [31:0] Bdq,
inout [3:0] Bdqs,
output [1:0] Bram_clkp,
output [1:0] Bram_clkn,
// I/O to RAM chip C
output Cras_out,
output Ccas_out,
output Cwr_out,
output [3:0] Cdm_out,
output [12:0] Caddr_out,
output [1:0] Cbank_out,
inout [31:0] Cdq,
inout [3:0] Cdqs,
output [1:0] Cram_clkp,
output [1:0] Cram_clkn,
// I/O to RAM chip D
output Dras_out,
output Dcas_out,
output Dwr_out,
output [3:0] Ddm_out,
output [12:0] Daddr_out,
output [1:0] Dbank_out,
inout [31:0] Ddq,
inout [3:0] Ddqs,
output [1:0] Dram_clkp,
output [1:0] Dram_clkn,
output mem_cke,
output mem_cs_,
// Hirose connector
// ...
// Note on video:
// Top DVI, top DAC, and TV chip share some signals
// Bottom DVI
output [11:0] bot_dvi_m_out,
output [11:0] bot_dvi_s_out,
output bot_dvi_m_clk,
output bot_dvi_s_clk,
output bot_dvi_vsync,
output bot_dvi_hsync,
output bot_dvi_de,
// Top DAC
output [29:0] top_dac_out,
output top_dac_sync,
output top_dac_de,
output top_dac_clk,
output top_dac_hsync,
output top_dac_vsync,
// Top DVI
// data shared with top_dac_out
output top_dvi_m_clk,
output top_dvi_s_clk,
output top_dvi_vsync,
output top_dvi_hsync,
output top_dvi_de,
// TV chip
// Make comments on shared signals...
// General-purpose connector (back end of board)
inout [63:0] gp_data,
inout [1:0] gp_other,
inout gp_clk,
// test outputs
// ...
);
endmodule
--
Timothy Normand Miller
http://www.cse.ohio-state.edu/~millerti
Open Graphics Project
_______________________________________________
Open-graphics mailing list
[email protected]
http://lists.duskglow.com/mailman/listinfo/open-graphics
List service provided by Duskglow Consulting, LLC (www.duskglow.com)
