Evening fellows,
So I'm looking at the pad rings and figuring some stuff out. As I've
figured it out, it's all about breaking out the different busses and
wires from the top module into different individual wires so we can map
them to the pins at the FPGA right? Somewhat like the constraint file
from the Xilinx work flow? Just want to know if I am on the right track
here :)
Now, if I've understood the task correctly, my next question is about
naming scheme. The logical way to continue would naturally be to name
the each individual pin in the pad ring accordingly to the name of the
corresponding pin found in the schematics[1]. However, this is where my
non-electrical engineering appears, and where I just want to be sure
before I start any major code writing. Consider Bank 3 at page 3 which
has something like this:
BRIDGE_CTRL[11] <==>-------N15| PR26A
Would the correct implementation map the Bridge Ctrl[11] to a wire named
N15 in the pad ring? Or is there another naming scheme that would be
favorable?
And while I'm at it, is it possible to get the schematics text in
another color than gray? I can hardly spot the text on my LCD monitor.
Regards,
Kenneth
[1] http://www.traversaltech.com/doc/DC-001-0001.pdf
--
Life on the earth might be expensive, but it
includes an annual free trip around the earth.
Kenneth Østby
http://langly.org
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