This one will require research, which I'll start on, but I'd like someone else to take responsibility for it.
Aside from perhaps a bit of work on I/O buffers, here's the main issue we need to address for PCI. For the Xilinx version, we have these: //synthesis attribute keep_hierarchy of mux0 is yes This indicates that a module that we have instantiated with the name mux0 must not be optimized through. The reason we need this has been described elsewhere. What we need to find out is the equivalent way to do this for Lattice chips. I think we select Synplicity as the synthesizer for Lattice. I've posted this, but let's not count on it: http://groups.google.com/group/comp.arch.fpga/browse_thread/thread/f289e39a2621d3cf#f2a1b773d6292bf0 -- Timothy Normand Miller http://www.cse.ohio-state.edu/~millerti Open Graphics Project _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
