On 12/16/07, Kenneth Ostby <[EMAIL PROTECTED]> wrote:
> I'm currently working on wiring the XP10 toplevel module together, and I
> started with the SPI interfaces. What I'm currently pondering upon is
> twofold. First would it make sense to separate the two command FIFOs to
> the each SPI. Currently, in the included patch I solved this by having a
> wide FIFO, but is better if I split it into two fifos for the read /
> write commands ?

Only one will ever happen at one time.  In this case, my solution is
to make a write fifo (with address and data), and then add extra flags
so that it also serves as a read request fifo.  This will save you the
logic of two request fifos and the muxing.

Also, one option we have for this, should we get short on space, is to
eliminate the write paths to the SPIs and the read path from the
Xilinx bitfile PROM.  Instead, we put in a dead-simple interface that
lets you twiddle the SPI control lines directly.  It's much slower
that way, but it requires almost no logic.

>
> Secondly, what should I connect the FIFO buffers to at the other side (
> the not SPI side )? The schema seen here[1] shows glue logic, but where
> is that located? Should this be done by microprogramming in the HQ?
> This would lead to more IO ports in the HQ.

There needs to be ports on the pci_address_decode module.  Requests
would come from there, and read data would come back to it.

>
> [1] http://www.cse.ohio-state.edu/~millerti/ogd1_vga_diagram.pdf
>
>
> --
> Life on the earth might be expensive, but it
> includes an annual free trip around the earth.
>
> Kenneth Østby
> http://langly.org
>
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-- 
Timothy Normand Miller
http://www.cse.ohio-state.edu/~millerti
Open Graphics Project
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