I've taken to using this as my reference for verilog: http://www.sutherland-hdl.com/on-line_ref_guide/vlog_ref_body.html
Section 19.0 describes the timescale directive functionally the same way as you describe it. `timescale 1ns / 1ps specifies a time step of 1 ns in the simulation with a precision of 3 decimal points, or 1ps. The #10 delay directive should the be interpreted as 10ns+-1ps, at least the way I read it. It could also mean 10ns+-10ps depending on how the implementation is done. Is it possible that it is this precision that is causing problems? If the delay is 10n-1ps then is it printing it as 99999ps? Or is it doing something even funkier? I'm at work right so I can't dig much deeper at the moment. Patrick M ----- Original Message ---- From: Timothy Normand Miller <[EMAIL PROTECTED]> To: gEDA developer mailing list <[EMAIL PROTECTED]>; Stephen Williams <[EMAIL PROTECTED]>; ogml <[email protected]> Sent: Thursday, December 20, 2007 11:21:45 AM Subject: [Open-graphics] Problem with timescale directive in Icarus? I don't use timescale much, so I could be just making a stupid mistake, but I'm getting unexpected behavior. Howard reports that he's seen this with ModelSim too, so maybe it's just us. Anyhow, I have this at the top of a couple of files: `timescale 1ns / 1ps My understanding is that this means that the time precision is 1ps, but if you do #10, for example, that still means 10ns. I'm finding that this isn't consistent, where some parts of my code are in the ns timescale and others are in the ps timescale. Anyone got any ideas? Below is some of my code. The clocks are being computed on the ns timescale, while all the delays in the initial block at the end appear to be in the ps timescale unless I comment out all of the timescale directives. module test_fifo; parameter fifo_depth = 256; parameter fifo_width = 256; parameter addr_bits = 8; reg RESET_N; reg CLOCK_IN; initial begin CLOCK_IN = 0; forever #5 CLOCK_IN = !CLOCK_IN; end reg CLOCK_OUT; initial begin CLOCK_OUT = 0; forever #4 CLOCK_OUT = !CLOCK_OUT; end wire [fifo_width-1:0] DOUTi; reg [fifo_width-1:0] DINi; reg ENQi, DEQi; wire VALIDi, FULLi, EMPTYi, FULLo, EMPTYo; wire [addr_bits:0] FREEi, COUNTi, FREEo, COUNTo; reg [fifo_width-1:0] expect_DOUT; initial begin $dumpfile( "test.vcd" ); $dumpvars; expect_DOUT = 0; ENQi = 0; DEQi = 0; RESET_N = 1; #20; RESET_N = 0; #20; RESET_N = 1; #20; DINi = 'hdeadbeef; ENQi = 1; #10; ENQi = 0; #100; DEQi = 1; #10; //DEQi = 0; #100; //$finish; DEQi = 1; ENQi = 1; for (DINi=0; DINi<1000; DINi = DINi + 1) begin #10; //ENQi = !ENQi; end ENQi = 0; #1000; $finish; end -- Timothy Normand Miller http://www.cse.ohio-state.edu/~millerti Open Graphics Project _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
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