On 12/22/07, [EMAIL PROTECTED] <[EMAIL PROTECTED]> wrote: > I am going through all the recently committed RTL code and testing it to > make sure it is parsable by iverilog. > Is there anyone else doing this as well? Is there something more important > (though I don't know what could be, > since this has to be done at some point) I can be doing?
If you want to do this kind of sanity checking, another thing you can do is run the code through the corresponding synthesizers. Don't bother with place&route, especially since you can't target the 3S4000 with the web pack. You can do the second-level modules (e.g. video controller wrapper). The top levels aren't going to synthesize yet probably, although you can hack at those a bit if you like. Mostly what we want here is warnings and info messages. For instance, size mismatches on wires connected to ports, signals missing from sensitivity lists, registers missing from the reset sections of sequential code, etc. Thanks! -- Timothy Normand Miller http://www.cse.ohio-state.edu/~millerti Open Graphics Project _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
