Index: trunk/rtl/oga1/s3/s3_top_level.v
===================================================================
--- trunk/rtl/oga1/s3/s3_top_level.v	(revision 208)
+++ trunk/rtl/oga1/s3/s3_top_level.v	(working copy)
@@ -15,7 +15,7 @@
 */
 
 
-Module Spartan3_top_level(
+module Spartan3_top_level(
     // Clock inputs
     // ...
     
@@ -117,7 +117,7 @@
     // General-purpose connector (back end of board)
     inout [63:0] gp_data, 
     inout [1:0] gp_other,
-    inout gp_clk,
+    inout gp_clk
     
     
     // test outputs
@@ -156,7 +156,7 @@
 wire br_mem_rdata_deq;
 
 
-module s3_bridge(
+s3_bridge U1(
     .clock(br_clock),
     .reset_(reset_),
     
@@ -292,7 +292,7 @@
     .reg_clock(reg_clock),
     .reg_addr(reg_addr),
     .reg_data(reg_data),
-    .reg_do_write(reg_do_write && reg_addr[...]),
+    .reg_do_write(reg_do_write && reg_addr[...]), // First controller
     
     // Read end of request queue from bridge
     // This is only a 32-bit interface
@@ -320,11 +320,11 @@
     
     // Write end of read return queue to video
     .vid0_rdata  (vid0_rdata_inA),
-    .vid0_rdata_enq (vid0_rdata_enqA)
+    .vid0_rdata_enq (vid0_rdata_enqA),
 
     // Write end of read return queue to video
     .vid1_rdata  (vid1_rdata_inA),
-    .vid1_rdata_enq (vid1_rdata_enqA)
+    .vid1_rdata_enq (vid1_rdata_enqA),
     
     // Memory controller
     .cmd_mem             (Acmd_inA),
@@ -430,7 +430,7 @@
 reg [24:0] vid0_addrA;
 reg [9:0] vid0_countA;
 reg vid0_validA, vid0_countingA;
-assign vid0_deq_all = !vid0_countingA && !vid0_countingB && ...;
+assign vid0_deq_all = !vid0_countingA; //&& !vid0_countingB && ...;
 always @(posedge mem_clock or negedge reset_) begin
     if (!reset_) begin
         vid0_addrA <= 0;
Index: trunk/rtl/oga1/s3/s3_bridge.v
===================================================================
--- trunk/rtl/oga1/s3/s3_bridge.v	(revision 208)
+++ trunk/rtl/oga1/s3/s3_bridge.v	(working copy)
@@ -28,7 +28,7 @@
     output reg bridge_busy,
     
     // Engine interface
-    output [15:0] eng_addr,
+    output reg [15:0] eng_addr,
     input [31:0] eng_rdata,
     output reg [31:0] eng_wdata,
     output reg eng_do_write,
@@ -172,7 +172,7 @@
             eng_wdata <= bridge_ad_in_d;
             eng_do_write <= target[TARGET_ENG];
         end
-        default:
+        default: begin
             eng_read_count <= 0;
             eng_addr <= 0;
         end
Index: trunk/rtl/oga1/s3/arbiter.v
===================================================================
--- trunk/rtl/oga1/s3/arbiter.v	(revision 208)
+++ trunk/rtl/oga1/s3/arbiter.v	(working copy)
@@ -71,13 +71,13 @@
     output vid1_rdata_enq,
     
     // Memory controller
-    output reg [2:0] cmd_mem,
-    output reg [1:0] bank_mem,
-    output reg [12:0] row_mem, 
-    output reg [12:0] col_mem,
-    output reg [63:0] wdata_mem,
-    output reg [7:0] wbytes_mem,
-    output reg [2:0] rtag_mem,
+    output [2:0] cmd_mem,
+    output [1:0] bank_mem,
+    output [12:0] row_mem, 
+    output [12:0] col_mem,
+    output [63:0] wdata_mem,
+    output [7:0] wbytes_mem,
+    output [2:0] rtag_mem,
     input busy_mem,
     
     input [63:0] rdata_mem, 
@@ -212,7 +212,7 @@
     end
 end
 
-
+wire vid_deq;
 assign br_deq = allow_pci && !memctl_busy;
 assign vid_deq = allow_video && !memctl_busy;
 assign refresh_deq = allow_refresh && !memctl_busy;
Index: trunk/rtl/oga1/xp10/spi_wrapper.v
===================================================================
--- trunk/rtl/oga1/xp10/spi_wrapper.v	(revision 208)
+++ trunk/rtl/oga1/xp10/spi_wrapper.v	(working copy)
@@ -10,9 +10,9 @@
 	input 			reset_,
 
 	/* Static input */
-	input[7:0]		write_command; 
-	input[7:0]		read_command; 
-	input			dummy;
+	input[7:0]		write_command, 
+	input[7:0]		read_command, 
+	input			dummy,
 
 	/* Commands in interface */
 	input[23:2]		address, 
@@ -54,7 +54,7 @@
 * FIFO. Could save a bus by doing it in the instantiation, 
 * but that's why we got optimizers.
 */
-assign spi_command_in = {data_in,address,be,do_read}
+assign spi_command_in = {data_in,address,be,do_read};
 
 /* FIFO for holding the SPI Commands */
 fifo_16 #(48) comm(
@@ -72,7 +72,7 @@
 );
 
 // Demultiplex the signals from the Command FIFO.
-assign spi_data_in	= spi_command_out[0:31] // 32
+assign spi_data_in	= spi_command_out[0:31]; // 32
 assign spi_address 	= spi_command_out[32:43]; // 21
 assign spi_be 		= spi_command_out[44:47]; // 4
 assign spi_do_read	= spi_command_out[48];	// 1
@@ -122,9 +122,9 @@
 
 /* Driving the SPI signals */
 assign SI 	= spi_si; 
-assign SO	= spi_so,
-assign CE_	= spi_ce_, 
-assign SCK	= spi_sck,
+assign SO	= spi_so;
+assign CE_	= spi_ce_; 
+assign SCK	= spi_sck;
 
 /* Insert logic here?  */
 
Index: trunk/rtl/oga1/xp10/pci_address_decode.v
===================================================================
--- trunk/rtl/oga1/xp10/pci_address_decode.v	(revision 208)
+++ trunk/rtl/oga1/xp10/pci_address_decode.v	(working copy)
@@ -101,7 +101,7 @@
         prom_req_enq <= 0;
     end else begin
         prom_addr_enq <= 0;
-        if (start_read && access_target[TARGET_PROM])
+        if (start_read && access_target[TARGET_PROM]) begin
             prom_req_addr <= read_address >> 2;
             prom_req_enq <= 1;
         end
@@ -193,7 +193,7 @@
                     doing_eng_read <= 0;
                     
                     br_command <= b_addr;
-                    br_flags <= access_target[...];
+                    br_flags <= access_target[...]; // Should be TARGET_MEM?
                     
                     if (start_write) begin
                         // We catch address early