On Monday 21 January 2008 20:51:02 Kenneth Ostby wrote: > Lourens Veen: > >The S3 part, I think I have everything in the XP10 covered. > > > >Looking at it again, I guess I mainly don't understand the > > connection between the bridge and the arbiter. There is only one > > command queue, but the read end seems to consist of four separate > > parallel FIFOs, and I don't understand why. > > Is it the the four different memory banks you wonder about? > "arb2br_rdata_outA" and so forth?
Yes. I understand that there are our memory banks, so it makes sense to have four FIFOs with return data, one for each of them. But then how come we only have one command queue? I can see sending the same command to each bank, but you'd have to send different data upon writing... Lourens
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