There was some change made to the file in the repository. Because of
those change now the Spartan 3 part of the design can pass synthesis. It
will also solve some of the problem encountered by those trying to
simulate that part.
Here is the Changelog:
--------------------------------------------------------------
Author: theosib
Date: 2008-02-06 21:24:25 +0100 (Wed, 06 Feb 2008)
New Revision: 273
Modified:
trunk/rtl/oga1/s3/s3_bridge.v
Log:
Added "eng_do_write <= 0" back to the register write block.
Modified: trunk/rtl/oga1/s3/s3_bridge.v
===================================================================
--- trunk/rtl/oga1/s3/s3_bridge.v 2008-02-06 20:13:06 UTC (rev 272)
+++ trunk/rtl/oga1/s3/s3_bridge.v 2008-02-06 20:24:25 UTC (rev 273)
@@ -189,13 +189,16 @@
// Engine register access
always @(posedge clock or negedge reset_) begin
- if (!reset_) begin
- eng_do_write <= 0;
- eng_read_count <= 0;
- eng_addr <= 0;
- eng_wdata <= 0;
- end else begin
- case (bridge_cmd_d)
+ if (!reset_) begin
+ eng_do_write <= 0;
+ eng_read_count <= 0;
+ eng_addr <= 0;
+ eng_wdata <= 0;
+ end else begin
+ // Default to zero. Pulsed to 1 only on other conditions.
+ eng_do_write <= 0;
+
+ case (bridge_cmd_d)
b_rcount: begin
// We ignore the actual read count, because
// it always has to be 1.
@@ -212,11 +215,11 @@
eng_read_count <= 0;
eng_addr <= 0;
end
- endcase
-
- if (eng_read_count) begin
- eng_read_count <= eng_read_count - 1;
- end
+ endcase
+
+ if (eng_read_count) begin
+ eng_read_count <= eng_read_count - 1;
+ end
end
end
----------------------------------------------------------------------------------------------------
Author: apouliot
Date: 2008-02-06 21:13:06 +0100 (Wed, 06 Feb 2008)
New Revision: 272
Modified:
trunk/rtl/oga1/s3/arbiter.v
trunk/rtl/oga1/s3/s3_bridge.v
trunk/rtl/oga1/s3/s3_top_level.v
trunk/rtl/vid_ctl/pixel_fetch.v
trunk/rtl/vid_ctl/vid_control.v
Log:
modification to make all the file pass synthesis using ISE
Mostly unconnected signal or some small typo
Modified: trunk/rtl/oga1/s3/arbiter.v
===================================================================
--- trunk/rtl/oga1/s3/arbiter.v 2008-02-06 03:30:35 UTC (rev 271)
+++ trunk/rtl/oga1/s3/arbiter.v 2008-02-06 20:13:06 UTC (rev 272)
@@ -212,6 +212,8 @@
end
end
+wire memctl_busy;
+wire allow_video;
assign br_deq = allow_pci && !busy_mem;
assign vid0_deq = allow_vid0 && !busy_mem;
Modified: trunk/rtl/oga1/s3/s3_bridge.v
===================================================================
--- trunk/rtl/oga1/s3/s3_bridge.v 2008-02-06 03:30:35 UTC (rev 271)
+++ trunk/rtl/oga1/s3/s3_bridge.v 2008-02-06 20:13:06 UTC (rev 272)
@@ -97,7 +97,7 @@
reg [6:0] rcount;
always @(posedge clock) begin
if (!mem_full) mem_enq <= 0;
- eng_do_write <= 0;
+ //eng_do_write <= 0;
case (bridge_cmd_d)
b_addr: begin
@@ -189,9 +189,13 @@
// Engine register access
always @(posedge clock or negedge reset_) begin
- eng_do_write <= 0;
-
- case (bridge_cmd_d)
+ if (!reset_) begin
+ eng_do_write <= 0;
+ eng_read_count <= 0;
+ eng_addr <= 0;
+ eng_wdata <= 0;
+ end else begin
+ case (bridge_cmd_d)
b_rcount: begin
// We ignore the actual read count, because
// it always has to be 1.
@@ -206,12 +210,13 @@
end
default: begin
eng_read_count <= 0;
- eng_addr <= 0;
+ eng_addr <= 0;
end
- endcase
+ endcase
- if (eng_read_count) begin
+ if (eng_read_count) begin
eng_read_count <= eng_read_count - 1;
+ end
end
end
Modified: trunk/rtl/oga1/s3/s3_top_level.v
===================================================================
--- trunk/rtl/oga1/s3/s3_top_level.v 2008-02-06 03:30:35 UTC (rev 271)
+++ trunk/rtl/oga1/s3/s3_top_level.v 2008-02-06 20:13:06 UTC (rev 272)
@@ -50,6 +50,7 @@
Copyright 2007, Timothy Miller - [EMAIL PROTECTED]
Copyright 2007, Nicholas Sinnott-Armstrong - [EMAIL PROTECTED]
Copyright 2007, Patrick McNamara - [EMAIL PROTECTED]
+ Copyright 2008, Andre Pouliot - [EMAIL PROTECTED]
Comments:
@@ -96,6 +97,9 @@
* vid0_clock
* vid1_clock
* reset_
+ These are now declared but would need to be well connected it's
+ a fast hack to verify that everything can pass a first synthesis
+
* Mismatches:
* eng_addr is [15:0], but memory_wrapper::reg_addr needs it to be [4:0]
The fix is that we need to provide [4:0] to memory_wrapper
@@ -116,7 +120,15 @@
module Spartan3_top_level(
// Clock inputs
- // ...
+ // Tempory hack to make everything pass synthesis
+ input mem_clock,//AP
+ input mem_clock_90,//AP
+ input mem_clock_rd,//AP
+ input vid0_clock,//AP
+ input vid1_clock,//AP
+
+ //reset
+ input reset_,//AP
// Bridge Interface
inout [31:0] bridge_ad,
@@ -230,10 +242,10 @@
// on data going from the S3 to the XP10 with respect to its internal
// clock!
wire br_clock;
-
+assign br_clock = bridge_clock;
//Bridge address/data lines. This is a tri-state multiplexed bus.
//This is the top level module output to the XP10
-wire [31:0] bridge_ad;
+//wire [31:0] bridge_ad;
//Both of these will end up connected to the bridge add/data lines.
//The output lines will be tri-stated when not in use. This is
//necessary to enable two way communications across the bridge.
@@ -251,6 +263,7 @@
//will not be driving lines when bridge_oe is asserted. In other words
//the XP10 side of the bridge will need to tri-state it's drivers when
//asserting bride_oe.
+wire bridge_oe;
assign bridge_ad = bridge_oe ? bridge_ad_out : 32'hzzzzzzzz;
@@ -305,12 +318,13 @@
wire br2arb_enq;
//FIFO full signal
wire br_cmd_fifo_full;
+//Tracks how much of the bridge to memory fifo is in use
+wire [3:0] br_cmd_fifo_mem_free;
//FIFO nearly full signal. Will assert when FIFO reaches 3/4 full
wire br_mem_nearly_full;
assign br_mem_nearly_full = &br_cmd_fifo_mem_free[3:2]; // 3/4 full
-//Tracks how much of the bridge to memory fifo is in use
-wire [3:0] br_cmd_fifo_mem_free;
+
//arbiter side FIFO signals
//memory address
wire [26:0] br2arb_addr_out;
@@ -335,6 +349,11 @@
//Pop top value out of FIFO into arbiter
wire arb2br_deq;
//Each memory controller has it's own dequeue signal.
+wire arb2br_deqA;
+wire arb2br_deqB;
+wire arb2br_deqC;
+wire arb2br_deqD;
+
wire [0:3] arb2br_deqs = {arb2br_deqA, arb2br_deqB, arb2br_deqC, arb2br_deqD};
//We have to select the appropriate deque signal based on the memory address.
//This should compile/synthesize into a 4-1 mux. This may need to be
@@ -381,7 +400,7 @@
// 27 + 64 + 8 + 2 = 101
//Bridge side of the FIFO -- "input"
wire [100:0] br2arb_word_in = {br2arb_addr_in, br2arb_data_in,
- br2bar_bytes_in, br2arb_do_write_in, br2arb_do_read_in};
+ br2arb_bytes_in, br2arb_do_write_in, br2arb_do_read_in};
//Arbiter side of the FIFO -- "output"
wire [100:0] br2arb_word_out;
assign {br2arb_addr_out, br2arb_data_out,
@@ -395,6 +414,12 @@
wire [9:0] vid0_count_in;
//video controller 0 memory read fifo has valid data pending
wire vid0_valid;
+//"Busy" signals from each of the memory controllers. They are asserted
+//when the controller is actively processing a memory request.
+wire vid0_countingA;
+wire vid0_countingB;
+wire vid0_countingC;
+wire vid0_countingD;
//If none of the memory controllers are still processing then we
//can pop the current value off since we are done with it.
wire vid0_deq = !vid0_countingA && !vid0_countingB &&
@@ -406,12 +431,6 @@
//of the memory controllers are currently servicing a read request then
//let's start a new one.
assign vid0_start = vid0_deq && vid0_valid;
-//"Busy" signals from each of the memory controllers. They are asserted
-//when the controller is actively processing a memory request.
-wire vid0_countingA;
-wire vid0_countingB;
-wire vid0_countingC;
-wire vid0_countingD;
//Response FIFO outputs from each of the memory controllers. These
//will be bundled together into a 256 bit video word for vc0
wire [63:0] vid0_rdataA;
@@ -435,6 +454,12 @@
wire [9:0] vid1_count_in;
//video controller 1 memory read fifo has valid data pending
wire vid1_valid;
+//"Busy" signals// from each of the memory controllers. They are asserted
+//when the controller is actively processing a memory request.
+wire vid1_countingA;
+wire vid1_countingB;
+wire vid1_countingC;
+wire vid1_countingD;
//If none of the memory controllers are still processing then we
//can pop the current value off since we are done with it.
wire vid1_deq = !vid1_countingA && !vid1_countingB &&
@@ -446,12 +471,6 @@
//of the memory controllers are currently servicing a read request then
//let's start a new one.
assign vid1_start = vid1_deq && vid1_valid;
-//"Busy" signals// from each of the memory controllers. They are asserted
-//when the controller is actively processing a memory request.
-wire vid1_countingA;
-wire vid1_countingB;
-wire vid1_countingC;
-wire vid1_countingD;
//Response FIFO outputs from each of the memory controllers. These
//will be bundled together into a 256 bit video word for vc1
wire [63:0] vid1_rdataA;
@@ -527,7 +546,7 @@
.mem_rdata_deqD(br2arb_rdata_deqD)
);
-async_fifo_16 #(101) bridge_cmd(
+async_fifo_16 #(101) bridge_cmd_fifo(
.reset(reset_),
.in_clock(br_clock),
Modified: trunk/rtl/vid_ctl/pixel_fetch.v
===================================================================
--- trunk/rtl/vid_ctl/pixel_fetch.v 2008-02-06 03:30:35 UTC (rev 271)
+++ trunk/rtl/vid_ctl/pixel_fetch.v 2008-02-06 20:13:06 UTC (rev 272)
@@ -117,7 +117,7 @@
count,
req_addr,
req_count,
- req_enq,
+ req_enq
);
input vid_clock;
Modified: trunk/rtl/vid_ctl/vid_control.v
===================================================================
--- trunk/rtl/vid_ctl/vid_control.v 2008-02-06 03:30:35 UTC (rev 271)
+++ trunk/rtl/vid_ctl/vid_control.v 2008-02-06 20:13:06 UTC (rev 272)
@@ -306,8 +306,8 @@
.inc (inc),
.count (fetch_count),
.req_addr (req_addr),
- .req_enq (req_enq),
- .req_count (req_count)
+ .req_count (req_count),
+ .req_enq (req_enq)
);
//Instatiate pixel send unit. Takes pixel data coming back from the
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