We have come to discover some interesting things that certain platforms will do that are legal with respect to the PCI spec. Specifically, it's possible to be doing a burst write where all of the byte-enabled are de-asserted for any of the transfers in the burst. In other words, the cycle on the bus does not transfer data and serves only to increment the address. We have actually encountered this happening.
For OGA's access to graphics memory, that is not a problem, because we pay attention to the byte enables. However, this IS a problem for writing to control registers. We completely ignore the byte enabled. This is justified because a byte write to a config register is simply (software) programmer error. However, it's completely legit to have ALL of the bytes deasserted (and we have to have no effects from it). I'm not sure we can toss out the write in the XP10, because that could throw off counters, so what I think we need to do is have the address decode logic in the S3 figure it out and discard the dummy write. -- Timothy Normand Miller http://www.cse.ohio-state.edu/~millerti Open Graphics Project _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
