On 4 Mar 2008, at 17:37, Timothy Normand Miller wrote:
Ok, here's how it works...
Interesting. I tried some numbers and it seems to get pretty close to whatever we need. I don't know if it's close enough, but if Howard says so.. ;)
So anyway, I figure we don't have this implemented yet, and it's time I get laughed at* for trying to write something in Verilog. See attached. *Any* comments are most welcome, I'm not even sure if I get the concept of wires completely yet. ;)
Note that what you need to generate isn't always the dot rate. The video controller is clocked at 1/2 or 1/4 the dot rate, depending on the mode (that is, if we're processing 2 or 4 pixels per cycle), but we then need 4x and 2x (maybe, I forget) multiples of that for the final stage that controls the transmitters directly.
The final stage isn't instantiated yet in the top module so I don't know what's needed there. For now I just ignored all this; let the vid_clock generate the highest clock needed and divide later. Since these numbers need to be generated only once the code figuring it out is something left for HQ / BIOS / driver.
Cheers, Michael www.projectvga.org * Experience is what you get when you don't get what you want.
vid_clock.v
Description: Binary data
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