Michael Meeuwisse wrote: > I'd like to help, but I'm somewhat busy atm. Which signals are > causing errors? If I had to guess it'd be divisor1_cur & divisor1_out > being resetted in the wrong process.
Yup. > If so, I can easily fix his, but > don't have the time right now to start up a machine with Webpack to > synthesize. The attached patch fixes this and synthesizes with WebPack. - Viktor Pracht -- GMX startet ShortView.de. Hier findest Du Leute mit Deinen Interessen! Jetzt dabei sein: http://www.shortview.de/[EMAIL PROTECTED]
--- clock_gen.v.old 2008-06-03 19:42:26.000000000 +0200 +++ clock_gen.v 2008-06-03 19:41:17.000000000 +0200 @@ -131,9 +131,7 @@ always @(posedge divisor0_in or negedge reset_) begin if(!reset_) begin divisor0_cur <= 0; - divisor1_cur <= 0; divisor0_out <= 0; - divisor1_out <= 0; toggle_odd <= 0; end else begin if(!divisor0_cur) begin @@ -176,18 +174,23 @@ defparam Vid_DCM.CLKFX_MULTIPLY = 48; // Divide the second time -always @(posedge divisor1_in) begin - if(!divisor1_cur) begin - divisor1_out = ~divisor1_out; - case(divisor1) - 2: divisor1_cur <= 4'b0000; // n/2 - 3: divisor1_cur <= 4'b0001; // n/4 - 4: divisor1_cur <= 4'b0010; // n/8 - 5: divisor1_cur <= 4'b0100; // n/16 - default: divisor1_cur <= 4'b1000; // n/32 - endcase - end else - divisor1_cur <= divisor1_cur - 1; +always @(posedge divisor1_in or negedge reset_) begin + if (!reset_) begin + divisor1_cur <= 0; + divisor1_out <= 0; + end else begin + if(!divisor1_cur) begin + divisor1_out <= ~divisor1_out; + case(divisor1) + 2: divisor1_cur <= 4'b0000; // n/2 + 3: divisor1_cur <= 4'b0001; // n/4 + 4: divisor1_cur <= 4'b0010; // n/8 + 5: divisor1_cur <= 4'b0100; // n/16 + default: divisor1_cur <= 4'b1000; // n/32 + endcase + end else + divisor1_cur <= divisor1_cur - 1; + end end // Output the result, mux from divisor1_in if divisor1 is set to 1
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