I've dropped in some of the changes for video clock generation. On Wed, Jun 4, 2008 at 5:44 PM, Timothy Normand Miller <[EMAIL PROTECTED]> wrote: > There are some pieces missing from video. Michael's clock_gen.v > appears to be to spec, although I haven't tested it properly. > > One problem is that its output is wired directly into the video logic. > In fact, the output from that should be the 4X video clock, and then > we need additional logic to divide it down. Moreover, that divide > logic must not simply divide the clocks. When dividing a 2X clock by > 2, we need two output signals; one is the 1X clock (through a BUFG), > and the other is a register in the 2X clock domain that indicates the > phase of the 1X clock (basically, just mirroring it). There is an > analogous thing for a 4X clock, where the phase bus is four 1-hots. I > can provide the proper dividers, but I'm going to need help wiring it > in. > > Secondly, there is no logic in there that actually connects the video > controllers to the pins. The two heads are different, so that logic > needs to go at the top level. I can provide that too, but again, I > need help wiring it in. > > Thanks. > > -- > Timothy Normand Miller > http://www.cse.ohio-state.edu/~millerti > Open Graphics Project >
-- Timothy Normand Miller http://www.cse.ohio-state.edu/~millerti Open Graphics Project _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
