Anyone have an active license for ispLever? I have a bunch of expired
installs of 6.0, and to install 7.x, I'm going to have to wait for
Lattice to get back to me with some "approval" or whatever. The
metacomments in the code are set up for Synplicity.
Here are the files you'll need to put together:
rtl/
oga1/s3/
pci_address_decode.v
spi_wrapper.v
xp10_bridge_wrapper.v
xp10_bridge.v
xp10_configure.v
xp10_top_level.v
lib/
divider.v
pci/
target_fsm_syn.v
config_space.v
fifos/
async_fifo_16.v
(possibly some other fifo)
spi_prom/
spi.v
I think that's it. The PCI clock needs to be constrained to at least
66MHz (start with that for now). Also, we don't adjust the phase on
the PCI clock, so there needs to be an indication to the back end what
kind of delay there is to the pin. For now, set it to 7ns. That is,
the PCI clock has 7ns of skew on it, meaning that certain PCI I/Os
need to have really tight constraints on them (I'm too tired to figure
out if that's input or output). The "ref_ck" is going to be 156.25MHz.
The bridge clock is supposed to be something like 90MHz as a function
of the PLL, but if the synthesizer doesn't figure it out, constrain
ALL of the bridge clock signals to 90MHz. In fact, "bridge_clock_rx"
is an input from the S3; constrain it to 90MHz also. Finally,
synthesizer doesn't figure out that "spi_clock" is exactly 1/8 of
ref_ck, then constrain it to 20MHz.
Once I get ispLever set up here, I'll get a copy of the synthesis
project from someone and go from there. Meanwhile, people can start
identifying timing violations. For any long path, I typically need to
know the names of all of the wires and gates that the path goes
through in order to figure what part of my code it corresponds to.
Thanks!
--
Timothy Normand Miller
http://www.cse.ohio-state.edu/~millerti
Open Graphics Project
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