On Mon, Jun 16, 2008 at 8:47 AM, Kenneth Ostby <[EMAIL PROTECTED]> wrote:
> Timothy Normand Miller:
>>On Fri, Jun 13, 2008 at 6:54 PM, Jared Putnam <[EMAIL PROTECTED]> wrote:
>>> --- On Fri, 6/13/08, Timothy Normand Miller <[EMAIL PROTECTED]> wrote:
>>>> These may be nothing, but they should be investigated:
>>> [unused pins]
>>>
>>> Did you ever get a tool put together to ensure that all module 
>>> instatiations use the right number of wires for each port?
>>
>>Not sure.  I think someone wrote one in Perl or was going to, but I
>>can't remember.  That would be a good sanity check.
>
> I did write a simple one in perl quite some time ago, however, when I
> saw that the icarus had a switch for it, I discontinued the development
> of it. Atm. I can't remember the name of the switch, but should be
> easy to find it in the icarus man page.

Well, anyhow, I've managed to fix all the warnings that are actually
problems.  Also, there were some problems with entries in the
constraints file not finding the nets they were associated with.
Turns out that some signals were getting ripped out because they were
duplicates of other signals.  I put in some metacomments to force them
not to be ripped out, and voila.

So, wrt the XP10, we still are stuck on the PCI clock skew issue, and
for the S3, we're blowing the memory clock period constraint.  The
latter is entirely an internal problem.  I have four different logic
blocks trying to pull from a single fifo, so when it's time to
dequeue, I have to make sure only to dequeue when the intended target
is ready to get the data.  That results in a loop from fifo out data
back into the dequeue signal.  The simplest fix is to have four
separate command fifos, but that's a massive waste of logic area.  But
then again, so are most of the the other options.


-- 
Timothy Normand Miller
http://www.cse.ohio-state.edu/~millerti
Open Graphics Project
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