In sequential logic with a reset, be sure to always include all target
registers in the reset block. Otherwise bugs will result. For
instance, this is bad:
always @(posedge clock or negedge reset_) begin
if (!reset_) begin
a <= 0;
end else begin
a <= input0;
b <= input1;
end
end
The signal 'b' isn't included in the reset block. This is bad in
general. But when using a global reset, it makes the Xilinx
synthesizer barf. This, I'm up late right now fixing bad reset
blocks.
BTW, if 'b' really does not need a reset, then move it into its own
sequential block:
always @(posedge clock) begin
b <= input1;
end
--
Timothy Normand Miller
http://www.cse.ohio-state.edu/~millerti
Open Graphics Project
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