On Mon, 20 Oct 2008 09:45:46 +0100, "Mark Marshall"
<[EMAIL PROTECTED]> said:
> Timothy Normand Miller wrote:
> > During POST, the PC is supposed to assign addresses to OGD1's various
> > memory regions.  It works fine for BAR0 and BAR1, but for some reason,
> > we end up with a zero in the EPROM BAR.  In simulation, if we write an
> > address to the EPROM BAR, it works fine, so we need some ideas as to
> > why the host might be rejecting our EPROM.  There are two things that
> > come to mind, but we don't see why they should matter.  One is that we
> > show up as a VGA-compatible non-graphics device.  This is probably a
> > mistake somewhere that we just haven't gotten around to fixing.  The
> > second thing is that our EPROM contents do not start with AA55 (or
> > 55AA or whatever the signature is).  Any other ideas?  At some point,
> > we'll have to hook up a PCI bus analyzer and watch the boot process to
> > try to get some insight into this.  Another idea is that since the
> > EPROM is blank, it's probably reading back all FF, which the host
> > might be interpreting as not being claimed by any device.  One thing
> > that might help is if we had a dummy BIOS image (that it should think
> > of as valid but which doesn't DO anything) to program in there.
> > 
> > Any ideas?
> > 
> Hi.
> 
> Have you got any further with this?  I was quite excited that you'd got 
> this far?

Hi all,

All of the discovery of pci devices and mapping of roms has to
be done by the main bios... And we happen to have available an
open source bios to look at ;)

I think examining this might be useful:

http://tracker.coreboot.org/trac/coreboot/browser/trunk/coreboot-v2/src/devices/pci_rom.c

Greetings,
    Alexander

> MM
> 
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