This release implements hardware texture mapping! Texture mapping is performed at the scanline level. I use 16 bit fixed point math for texture coordinates in the fpga. Textures are the same 256x256 size as demonstrated in Release #3's software demo.
I fixed the bug that created the incorrect color distribution and black rectangles in the "Utah Spinner" demo. I had specified the pins on the fpga output lines for the green and blue colors in the reverse significant bit order. I added a 32 bit data 8 bit address control bus that is used to drive the functional units. The epp control unit has been gutted and now only drives this control bus, rather than the old design that effectively replicated the registers used in the functional units as inputs. This change saved a bunch of gates. This change also reduces the already very low parallel port command bandwidth, but it leaves the TVC with a pretty clean internal structure that is also not tied to an 8 bit wide command bus. The problems with the texture mapping demonstrated when the textures are reversed are not memory controller related, but rather are due (I think) to a problem in the texture coordinate signed/unsigned fixed point math. I have not looked very deeply into this problem yet. There are oodles of bugs in the memory controller that I still have no intention of fixing until I move to a different memory type. Xilinx's webpack 10.1 sp3 is working great under Slackware 12.2 using Digilent's parallel jtag cable and the libusb-driver. I'm running ISE over a remote X11 connection to my main workstation. It works perfectly (and better than under win2k). To download TVC release #4 see http://www.johnculp.net/tvc.html I've got a couple new videos up showing the somewhat fixed utah teapot demo and the new texture mapping demo. -John _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
