[To give context for the mailing list, a 'fake' access is where we allow indirect access to some regular memory or engine space in OGD1, but indirectly through PCI config space. This allows us to do setup before we're able to map BARs or when we can't do it anyway, like when in real mode, in BIOS.]
We had too much trouble getting fake writes to hold based on can_write. That is, if something was holding up the chip's ability to handle writes, we wanted fake writes to wait the same as any other kind of write. But that proved too challenging, so we're doing something different. Now, when you make a fake write, you must then poll another cfg register and wait for it to go to zero before you can move on and do anything else (and by anything, I mean ANYTHING, reads/writes to any BAR). Here's the relevant part of the memory map now (cfg addresses in decimal): 68 -- fake write address 72 -- fake write target 76 -- fake write data, with auto-increment on the address 80 -- fake write data, with NO auto-increment (like for loading HQ) 84 -- fake write pending status (read) 88 -- fake read address 92 -- fake read data Note that a write to 88 is the _trigger_ to cause a read of a local XP10 lower1k engine space register. You must write that every time you want to read. This causes the read to happen on the following clock cycle, loading the data into a holding register, and that register is only loaded as a result of the write to 88. There's some pipelining on this, but I think there's enough time during the address decode phase of the read transaction for this to compete. -- Timothy Normand Miller http://www.cse.ohio-state.edu/~millerti Open Graphics Project _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
