Hi.
One of the things that I've not been too keen on in the verilog source
is the multiple definitions of the different targets. This is made
worse by the fact that the targets are actually different in different
places (sometimes config is 0, other times engine registers are zero).
Here is a simple patch that hopefully corrects for that. It adds
definitions for each bit the the target register to a verilog file in
the include directory, and then uses these bits throughout. I've also
rearranged the targets so that the four common to everything are in the
low bits, therefore there should be no "target renumbering".
I've not checked it in because I have no way of testing it. What do you
guys think to such a patch?
(I've also moved the bridge commands into the include file).
MM
PS.
I've just noticed that there's a change in fifos/async_video_fifo_DxW.v
in this patch. I won't check this in, it's just that the old line was
crashing iverilog?
Index: include/internal.txt
===================================================================
--- include/internal.txt (revision 516)
+++ include/internal.txt (working copy)
@@ -83,13 +83,13 @@
#
# These are used in the XP10 and in the communication between the XP10
# and the host.
-REG_TYPE PCI_TARGET
-REG_BIT 0 RW CFG
-REG_BIT 1 RW ENG
-REG_BIT 2 RW MEM
-REG_BIT 3 RW VMEM
-REG_BIT 4 RW IO
-REG_BIT 5 RW PROM
+REG_TYPE TARGET
+REG_BIT 0 RW ENG
+REG_BIT 1 RW MEM
+REG_BIT 2 RW VMEM
+REG_BIT 3 RW IO
+REG_BIT 4 RW PROM
+REG_BIT 5 RW CFG
REG_TYPE_ENDS
# Bridge Targets
Index: include/oga1_defs.v
===================================================================
--- include/oga1_defs.v (revision 516)
+++ include/oga1_defs.v (working copy)
@@ -73,5 +73,26 @@
// Mark Marshall
// These should come from the SIG
-parameter PCI_VENDOR_ID_OGP = 16'h1227;
+parameter PCI_VENDOR_ID_OGP = 16'h1227;
parameter PCI_DEVICE_ID_OGD1 = 16'h0000;
+
+// These are the targets. The same order is now used on both sides of
+// the bridge.
+parameter TARGET_ENG_MASK = 6'h01;
+parameter TARGET_ENG_POSN = 3'd0;
+parameter TARGET_MEM_MASK = 6'h02;
+parameter TARGET_MEM_POSN = 3'd1;
+parameter TARGET_VMEM_MASK = 6'h03;
+parameter TARGET_VMEM_POSN = 3'd2;
+parameter TARGET_IO_MASK = 6'h08;
+parameter TARGET_IO_POSN = 3'd3;
+parameter TARGET_PROM_MASK = 6'h10;
+parameter TARGET_PROM_POSN = 3'd4;
+parameter TARGET_CFG_MASK = 6'h20;
+parameter TARGET_CFG_POSN = 3'd5;
+
+// These are the commands sent over the bridge
+parameter BRIDGE_COMMAND_IDLE = 2'h0;
+parameter BRIDGE_COMMAND_ADDR = 2'h1;
+parameter BRIDGE_COMMAND_RCOUNT = 2'h2;
+parameter BRIDGE_COMMAND_WRITE = 2'h3;
Index: fifos/async_video_fifo_DxW.v
===================================================================
--- fifos/async_video_fifo_DxW.v (revision 516)
+++ fifos/async_video_fifo_DxW.v (working copy)
@@ -93,7 +93,11 @@
// Grab output data into register
// XST will infer sync read from this
always @(posedge oCLOCK) begin
- oDOUT <= fifo_data[oDEQ ? oheadp1 : ohead];
+ //oDOUT <= fifo_data[oDEQ ? oheadp1 : ohead];
+ if (oDEQ)
+ oDOUT <= fifo_data[oheadp1];
+ else
+ oDOUT <= fifo_data[ohead];
end
Index: oga1/s3/s3_bridge.v
===================================================================
--- oga1/s3/s3_bridge.v (revision 516)
+++ oga1/s3/s3_bridge.v (working copy)
@@ -109,20 +109,9 @@
output reg test
);
+`include "oga1_defs.v"
-// Commands -- move to header file!
-parameter b_idle = 0;
-parameter b_addr = 1;
-parameter b_rcount = 2;
-parameter b_write = 3;
-
-// These target numbers are different from in the XP10
-parameter TARGET_ENG=0;
-parameter TARGET_MEM=1;
-
-
-
// Busy
always @(posedge clock) begin
bridge_busy <= mem_nearly_full;
@@ -150,12 +139,12 @@
//eng_do_write <= 0;
case (bridge_cmd_d)
- b_addr: begin
+ BRIDGE_COMMAND_ADDR: begin
address <= bridge_ad_in_d[29:2]; // Discard byte offset
target <= bridge_flags_d;
end
- b_rcount: rcount <= bridge_ad_in_d;
- b_write: begin
+ BRIDGE_COMMAND_RCOUNT: rcount <= bridge_ad_in_d;
+ BRIDGE_COMMAND_WRITE: begin
mem_addr <= address[27:1]; // Discard dword offset
// Cheat by not combining adjacent writes
// This should be easy to optimize later
@@ -167,7 +156,7 @@
mem_bytes[7:4] <= {4{address[0]}} & bridge_flags_d;
mem_do_write <= 1;
mem_do_read <= 0;
- mem_enq <= target[TARGET_MEM];
+ mem_enq <= target[TARGET_MEM_POSN];
end
endcase
@@ -175,7 +164,7 @@
mem_addr <= address[27:1]; // Discard dword offset
mem_do_write <= 0;
mem_do_read <= 1;
- mem_enq <= target[TARGET_MEM];
+ mem_enq <= target[TARGET_MEM_POSN];
address[6:1] <= address[6:1] + 1;
rcount[6:1] <= rcount[6:1] - 1;
@@ -198,7 +187,7 @@
mem_rdata_validD, mem_rdata_validD};
always @(posedge clock) begin
- if (target[TARGET_MEM]) begin
+ if (target[TARGET_MEM_POSN]) begin
case (return_slice)
0: bridge_ad_out <= mem_rdataA[31:0];
1: bridge_ad_out <= mem_rdataA[63:32];
@@ -218,7 +207,7 @@
reg [7:0] tdo;
always @(posedge clock) begin
- if (target[TARGET_MEM]) begin
+ if (target[TARGET_MEM_POSN]) begin
case (return_slice)
0: tdo <= mem_rdataA[31:0];
1: tdo <= mem_rdataA[63:32];
@@ -248,7 +237,7 @@
bridge_rdata_valid <= 0;
tdv <= 0;
end else begin
- if (bridge_cmd_d == b_rcount) begin
+ if (bridge_cmd_d == BRIDGE_COMMAND_RCOUNT) begin
return_slice <= 0;
end
@@ -259,7 +248,7 @@
// BIG BIG, MASSIVE NOTE: Need to make sure this
// matches up with both PCI writes and how other components
// (engine, video) want memory to be organized!
- if (target[TARGET_MEM] && rdata_valid[return_slice]) begin
+ if (target[TARGET_MEM_POSN] && rdata_valid[return_slice]) begin
bridge_oe <= 1;
/*case (return_slice)
0: bridge_ad_out <= mem_rdataA[31:0];
@@ -313,7 +302,7 @@
always @(posedge clock) begin
if (eng_do_write) $display("S3 Writing 0x%x to 0x%x", eng_wdata, eng_addr);
if (eng_read_count == 1) $display("S3 Got read data 0x%x", eng_rdata);
- if (bridge_cmd_d == b_rcount) $display("S3 Requesting engine read at
0x%x", address);
+ if (bridge_cmd_d == BRIDGE_COMMAND_RCOUNT) $display("S3 Requesting engine
read at 0x%x", address);
end
// synopsys translate_on
@@ -341,18 +330,18 @@
eng_do_read <= 0;
case (bridge_cmd_d)
- b_rcount: begin
+ BRIDGE_COMMAND_RCOUNT: begin
// We ignore the actual read count, because
// it always has to be 1.
eng_addr <= address;
// Start delay counter at 3
- eng_read_count <= {2{target[TARGET_ENG]}};
- eng_do_read <= target[TARGET_ENG];
+ eng_read_count <= {2{target[TARGET_ENG_POSN]}};
+ eng_do_read <= target[TARGET_ENG_POSN];
end
- b_write: begin
+ BRIDGE_COMMAND_WRITE: begin
eng_addr <= address;
eng_wdata <= bridge_ad_in_d;
- eng_do_write <= target[TARGET_ENG];
+ eng_do_write <= target[TARGET_ENG_POSN];
end
default: begin
eng_read_count <= 0;
Index: oga1/xp10/pci_address_decode.v
===================================================================
--- oga1/xp10/pci_address_decode.v (revision 516)
+++ oga1/xp10/pci_address_decode.v (working copy)
@@ -188,6 +188,7 @@
output reg [2:0] interrupt_enable
);
+`include "oga1_defs.v"
// DDC section. Move to submodule?
reg top_ddc_clk_o, top_ddc_data_o;
@@ -224,26 +225,10 @@
wire do_write = do_write_i || do_fake_write;
-// Access targets. Move into header!
-parameter TARGET_CFG=0;
-parameter TARGET_ENG=1;
-parameter TARGET_MEM=2;
-parameter TARGET_VMEM=3;
-parameter TARGET_IO=4;
-parameter TARGET_PROM=5;
-
-
reg cache_enabled;
-// Commands -- move to header file!
-parameter b_idle = 0;
-parameter b_addr = 1;
-parameter b_rcount = 2;
-parameter b_write = 3;
-
-
wire [31:0] cfg_read_data;
wire cfg_read_valid;
@@ -284,7 +269,7 @@
end else begin
bprom_do_read <= 0;
// Make sure PROM accesses are always one-shot!
- if (start_read && access_target[TARGET_PROM] && !bprom_busy) begin
+ if (start_read && access_target[TARGET_PROM_POSN] && !bprom_busy) begin
bprom_read_addr <= read_address[23:2];
bprom_do_read <= 1;
end
@@ -295,13 +280,13 @@
// Divide the address space for reg reads between XP10 and S3
wire lower_1k = read_address[17:12] == 0;
-wire eng_xp10 = access_target[TARGET_ENG] && lower_1k;
-wire eng_s3 = access_target[TARGET_ENG] && !lower_1k;
+wire eng_xp10 = access_target[TARGET_ENG_POSN] && lower_1k;
+wire eng_s3 = access_target[TARGET_ENG_POSN] && !lower_1k;
wire read_cache = cache_enabled &&
- (access_target[TARGET_MEM] || access_target[TARGET_VMEM]);
+ (access_target[TARGET_MEM_POSN] || access_target[TARGET_VMEM_POSN]);
wire read_direct = eng_s3 ||
- (!cache_enabled && (access_target[TARGET_MEM] ||
access_target[TARGET_VMEM]));
+ (!cache_enabled && (access_target[TARGET_MEM_POSN] ||
access_target[TARGET_VMEM_POSN]));
wire read_local = eng_xp10;
@@ -426,19 +411,19 @@
({32{read_cache}} & cache_data) |
({32{read_direct}} & cache_eng_data) |
({32{read_local}} & local_reg_data) |
- ({32{access_target[TARGET_PROM]}} & bprom_read_data) |
- ({32{access_target[TARGET_CFG]}} & cfg_read_data);
+ ({32{access_target[TARGET_PROM_POSN]}} & bprom_read_data) |
+ ({32{access_target[TARGET_CFG_POSN]}} & cfg_read_data);
assign read_valid =
(read_cache && cache_hit && doing_read) ||
(read_direct && cache_eng_valid) ||
(read_local) ||
- (access_target[TARGET_PROM] && bprom_read_valid) ||
- (access_target[TARGET_CFG] && cfg_read_valid);
+ (access_target[TARGET_PROM_POSN] && bprom_read_valid) ||
+ (access_target[TARGET_CFG_POSN] && cfg_read_valid);
-wire bridge_access = (access_target[TARGET_MEM] || access_target[TARGET_VMEM]
|| eng_s3);
+wire bridge_access = (access_target[TARGET_MEM_POSN] ||
access_target[TARGET_VMEM_POSN] || eng_s3);
wire mem_read = read_cache && !cache_hit;
@@ -452,7 +437,7 @@
// When to dequeue read return data
assign br_deq_read = doing_eng_read_s3 ||
doing_cache_load;
-assign bprom_read_deq = access_target[TARGET_PROM] && deq_read;
+assign bprom_read_deq = access_target[TARGET_PROM_POSN] && deq_read;
@@ -467,9 +452,9 @@
// Can write freely to CFG
// MEM and ENG require that the bridge command fifo have a free entry
-assign can_write = access_target[TARGET_CFG] ||
+assign can_write = access_target[TARGET_CFG_POSN] ||
eng_xp10 ||
- access_target[TARGET_PROM] || // need to discard PROM writes
+ access_target[TARGET_PROM_POSN] || // need to discard PROM writes
(bridge_access && (!br_full || !br_enq) && state==s_write);
@@ -482,7 +467,7 @@
cache_valid <= 0;
br_enq <= 0;
br_flags <= 0;
- br_command <= 0;
+ br_command <= BRIDGE_COMMAND_IDLE;
load_counter <= 0;
cache_replace <= 0;
cache_load_addr <= 0;
@@ -493,7 +478,7 @@
end else begin
// Wipe the cache on any memory write. We could do
// write-through later.
- if (doing_write && (access_target[TARGET_MEM] ||
access_target[TARGET_VMEM])) begin
+ if (doing_write && (access_target[TARGET_MEM_POSN] ||
access_target[TARGET_VMEM_POSN])) begin
cache_valid <= 0;
end
@@ -509,8 +494,8 @@
doing_cache_load <= 0;
doing_eng_read_s3 <= 0;
- br_command <= b_addr;
- br_flags <= access_target[4:1];
+ br_command <= BRIDGE_COMMAND_ADDR;
+ br_flags <= access_target[3:0];
if (start_write) begin
// We catch address early
@@ -547,7 +532,7 @@
s_read_count: begin
// Sent read address, now need to send read count
- br_command <= b_rcount;
+ br_command <= BRIDGE_COMMAND_RCOUNT;
br_data <= load_counter;
br_enq <= 1;
@@ -574,7 +559,7 @@
br_data <= write_data;
br_flags <= write_bytes;
br_enq <= do_write;
- br_command <= b_write;
+ br_command <= BRIDGE_COMMAND_WRITE;
if (end_write) state <= s_idle;
end
@@ -655,7 +640,7 @@
.write_address (write_address_i[7:0]),
.write_bytes (write_bytes_i),
.write_data (write_data_i),
- .do_write (do_write_i && access_target_i[0]),
+ .do_write (do_write_i && access_target_i[TARGET_CFG_POSN]),
.can_write (can_write),
.decode_address (decode_address),
Index: oga1/xp10/xp10_top_level.v
===================================================================
--- oga1/xp10/xp10_top_level.v (revision 516)
+++ oga1/xp10/xp10_top_level.v (working copy)
@@ -468,8 +468,8 @@
.bridge_rdata_valid (bridge_rdata_valid),
.bridge_busy (bridge_busy),
- .bridge_clock_2x (bridge_clock_2x),
- .test (test[0])
+ .bridge_clock_2x (bridge_clock_2x)//,
+ //.test (test[0])
);
Index: oga1/xp10/xp10_bridge.v
===================================================================
--- oga1/xp10/xp10_bridge.v (revision 516)
+++ oga1/xp10/xp10_bridge.v (working copy)
@@ -135,15 +135,9 @@
);
+`include "oga1_defs.v"
-// Commands -- move to header file!
-parameter b_idle = 0;
-parameter b_addr = 1;
-parameter b_rcount = 2;
-parameter b_write = 3;
-
-
// Busy signals
reg s3busy;
always @(posedge bridge_clock_tx) s3busy <= bridge_busy;
@@ -179,15 +173,7 @@
end
end
-
-
-
-
-
-
-
-
always @(posedge bridge_clock_tx or negedge reset_) begin
if (!reset_) begin
busy_reading <= 0;
@@ -199,12 +185,12 @@
bridge_oe <= !busy_reading; // first cycle after rcount
// Address, read count, or write data
bridge_ad_out <= data_in;
- bridge_cmd <= command_in & {2{deq_in && valid_in}};
+ bridge_cmd <= (deq_in && valid_in) ? command_in : BRIDGE_COMMAND_IDLE;
// Write bytes or access target
bridge_flags <= flags_in;
if (read_count == 0) busy_reading <= 0;
- if (deq_in && valid_in && command_in == b_rcount) begin
+ if (deq_in && valid_in && command_in == BRIDGE_COMMAND_RCOUNT) begin
read_count <= data_in;
busy_reading <= 1;
Index: oga1/xp10/xp10_bridge_wrapper.v
===================================================================
--- oga1/xp10/xp10_bridge_wrapper.v (revision 516)
+++ oga1/xp10/xp10_bridge_wrapper.v (working copy)
@@ -99,6 +99,8 @@
wire [1:0] command_out;
wire [31:0] data_out;
wire [3:0] flags_out;
+
+`include "oga1_defs.v"
// Command fifo from PCI to HQ
@@ -376,11 +378,7 @@
parameter MEM_READQ_AVAIL = MEM_BASE + 9'h02;
parameter MEM_READQ_DATA = MEM_BASE + 9'h03;
-// Bridge Commands
-parameter BR_CMD_IDLE = 0;
-parameter BR_CMD_ADDR = 1;
-parameter BR_CMD_RCOUNT = 2;
-parameter BR_CMD_WRITE = 3;
+`include "oga1_defs.v"
/* NOTES
The way async_fifo_16_count is designed, the count is often an
underestimate.
@@ -473,7 +471,7 @@
always @(posedge clock) begin
hq2br_cmd_data <= hqio_outport;
- hq2br_cmd_type <= BR_CMD_IDLE;
+ hq2br_cmd_type <= BRIDGE_COMMAND_IDLE;
hq2br_cmd_flags <= hqio_addr[3:0];
hq2pci_read_enq <= 0;
hq2pci_read_data <= hqio_outport;
@@ -481,20 +479,20 @@
// Assign enqueue and command type if port write.
if (hqio_enable_out) begin
if (hqio_addr[8:4] == (MEM_SEND_DATA_0000 >> 4))
- hq2br_cmd_type <= BR_CMD_WRITE;
+ hq2br_cmd_type <= BRIDGE_COMMAND_WRITE;
case (hqio_addr)
PCI_TR_DATA:
hq2pci_read_enq <= 1;
MEM_SEND_ADDR_MEM: begin
- hq2br_cmd_type <= BR_CMD_ADDR;
- hq2br_cmd_flags <= 4'b0010;
+ hq2br_cmd_type <= BRIDGE_COMMAND_ADDR;
+ hq2br_cmd_flags <= TARGET_MEM_MASK;
end
MEM_SEND_ADDR_ENG: begin
- hq2br_cmd_type <= BR_CMD_ADDR;
- hq2br_cmd_flags <= 4'b0001;
+ hq2br_cmd_type <= BRIDGE_COMMAND_ADDR;
+ hq2br_cmd_flags <= TARGET_ENG_MASK;
end
MEM_SEND_READ_COUNT:
- hq2br_cmd_type <= BR_CMD_RCOUNT;
+ hq2br_cmd_type <= BRIDGE_COMMAND_RCOUNT;
endcase
end
Index: pci/target_fsm.v
===================================================================
--- pci/target_fsm.v (revision 516)
+++ pci/target_fsm.v (working copy)
@@ -135,14 +135,8 @@
-// Access target bits
-parameter TARGET_CFG=0;
-parameter TARGET_ENG=1;
-parameter TARGET_MEM=2;
-parameter TARGET_PROM=3;
-parameter TARGET_IO=4;
+`include "oga1_defs.v"
-
input clock, _reset;
input [31:0] ad_i;
@@ -162,14 +156,14 @@
input [31:0] read_data;
output [31:0] write_data;
output [3:0] write_bytes;
-output [4:0] access_target;
+output [5:0] access_target;
output deq_read, start_read, end_read;
output do_write;
input read_valid;
input can_write;
reg [31:0] write_data;
reg [3:0] write_bytes;
-reg [4:0] access_target;
+reg [5:0] access_target;
reg deq_read, start_read, end_read;
reg do_write;
@@ -289,9 +283,12 @@
if (config_space) begin
address_valid = address[1:0]==0;
end else if (io_space) begin
- address_valid = decode_target[TARGET_IO];
+ address_valid = decode_target[TARGET_IO_POSN];
end else if (mem_space) begin
- address_valid = |decode_target[3:1];
+ address_valid = decode_target[TARGET_ENG_POSN] |
+ decode_target[TARGET_MEM_POSN] |
+ decode_target[TARGET_VMEM_POSN] |
+ decode_target[TARGET_PROM_POSN];
end
end
@@ -392,9 +389,12 @@
read_hold <= 0;
ad_o <= read_data;
- access_target[3:1] <= decode_target[3:1];
- access_target[4] <= decode_target[4] && io_space;
- access_target[0] <= config_space;
+ access_target[TARGET_ENG_POSN] <=
decode_target[TARGET_ENG_POSN];
+ access_target[TARGET_MEM_POSN] <=
decode_target[TARGET_MEM_POSN];
+ access_target[TARGET_VMEM_POSN] <=
decode_target[TARGET_VMEM_POSN];
+ access_target[TARGET_IO_POSN] <= decode_target[TARGET_IO_POSN]
&& io_space;
+ access_target[TARGET_PROM_POSN] <=
decode_target[TARGET_PROM_POSN];
+ access_target[TARGET_CFG_POSN] <= config_space;
end
s_decode1w: begin
@@ -415,9 +415,12 @@
stop_o <= !((can_write || !do_write) && last_phase);
devsel_o <= !address_valid;
- access_target[3:1] <= decode_target[3:1];
- access_target[4] <= decode_target[4] && io_space;
- access_target[0] <= config_space;
+ access_target[TARGET_ENG_POSN] <=
decode_target[TARGET_ENG_POSN];
+ access_target[TARGET_MEM_POSN] <=
decode_target[TARGET_MEM_POSN];
+ access_target[TARGET_VMEM_POSN] <=
decode_target[TARGET_VMEM_POSN];
+ access_target[TARGET_IO_POSN] <= decode_target[TARGET_IO_POSN]
&& io_space;
+ access_target[TARGET_PROM_POSN] <=
decode_target[TARGET_PROM_POSN];
+ access_target[TARGET_CFG_POSN] <= config_space;
end
s_read: begin
Index: pci/pci_top.v
===================================================================
--- pci/pci_top.v (revision 516)
+++ pci/pci_top.v (working copy)
@@ -151,16 +151,17 @@
assign cbe_oe = 0;
assign frame_oe = 0;
+`include "oga1_defs.v"
wire [31:0] read_address, read_data, write_address, write_data;
wire do_write;
wire can_write;
wire [3:0] write_bytes;
-wire [4:0] access_target;
+wire [5:0] access_target;
wire start_read, end_read, read_valid, deq_read;
wire [31:0] decode_address;
-wire [4:0] decode_target;
+wire [5:0] decode_target;
wire set_parity_error, parity_error_enable;
@@ -233,7 +234,7 @@
.write_address (write_address[7:0]),
.write_bytes (write_bytes),
.write_data (write_data),
- .do_write (do_write && access_target[0]),
+ .do_write (do_write && access_target[TARGET_CFG_POSN]),
.decode_address (decode_address),
.decode_target (decode_target),
@@ -313,7 +314,10 @@
always @(posedge clock) begin
- if (do_write && access_target[4:1] && can_write) begin
+ if (do_write && (access_target[TARGET_ENG_POSN] ||
+ access_target[TARGET_MEM_POSN] ||
+ access_target[TARGET_VMEM_POSN] ||
+ access_target[TARGET_IO_POSN]) && can_write) begin
if (write_bytes[0]) memory0[write_address[7:2]] <= write_data[7:0];
if (write_bytes[1]) memory1[write_address[7:2]] <= write_data[15:8];
if (write_bytes[2]) memory2[write_address[7:2]] <= write_data[23:16];
@@ -322,8 +326,8 @@
end
-assign read_data = access_target[0] ? cfg_read_data : mem_read_data;
-assign read_valid = access_target[0] ? cfg_read_valid : mem_read_valid;
+assign read_data = access_target[TARGET_CFG_POSN] ? cfg_read_data :
mem_read_data;
+assign read_valid = access_target[TARGET_CFG_POSN] ? cfg_read_valid :
mem_read_valid;
reg [1:0] can_write_r;
@@ -337,6 +341,6 @@
can_write_r <= 1;
end
-assign can_write = can_write_r==0 || access_target[0];
+assign can_write = can_write_r==0 || access_target[TARGET_CFG_POSN];
endmodule
Index: pci/config_space.v
===================================================================
--- pci/config_space.v (revision 516)
+++ pci/config_space.v (working copy)
@@ -132,10 +132,11 @@
reg read_valid;
output parity_error_enable;
-
+`include "oga1_defs.v"
+
input [31:0] decode_address;
output [5:0] decode_target;
-assign decode_target[0] = 0;
+assign decode_target[TARGET_CFG_POSN] = 0;
input class_other, class_xga, class_3d, allow_66mhz;
@@ -161,7 +162,7 @@
reg [29:0] fake_read_addr;
output do_fake_read;
reg do_fake_read;
-input fake_read_data;
+input [31:0] fake_read_data;
// BAR enables
@@ -182,7 +183,7 @@
//wire BAR2_en;
reg io_space_enable;
-wire BAR0_en, BAR1_en, EROM_en, VGAI_en, MDA_en, CGA_en;
+wire BAR0_en, BAR1_en, EROM_en, VGAI_en, MDA_en, CGA_en, VMEM_en;
assign BAR0_en = mem_decode_en_b[0];
assign BAR1_en = mem_decode_en_b[1];
//assign BAR2_en = mem_decode_en_b[2];
@@ -240,12 +241,13 @@
VGAI_v = VGAI_v && (address_r[31:7] == 7);
end
+assign decode_target[TARGET_ENG_POSN] = BAR0_v;
+assign decode_target[TARGET_MEM_POSN] = BAR1_v;
+assign decode_target[TARGET_VMEM_POSN] = VMEM_v;
+assign decode_target[TARGET_IO_POSN] = VGAI_v;
+assign decode_target[TARGET_PROM_POSN] = EROM_v;
-assign decode_target[5:1] = {EROM_v, VGAI_v, VMEM_v, BAR1_v, BAR0_v};
-
-
-
reg received_master_abort, received_target_abort, signaled_target_abort;
reg master_data_parity_error, vga_palette_snoop;
reg parity_error_enable, parity_error;
Index: pci/target_fsm_syn.v
===================================================================
--- pci/target_fsm_syn.v (revision 516)
+++ pci/target_fsm_syn.v (working copy)
@@ -139,16 +139,9 @@
);
+`include "oga1_defs.v"
-// Access target bits
-parameter TARGET_CFG=0;
-parameter TARGET_ENG=1;
-parameter TARGET_MEM=2;
-parameter TARGET_VMEM=3;
-parameter TARGET_IO=4;
-parameter TARGET_PROM=5;
-
input clock, _reset;
input [31:0] ad_i;
@@ -391,11 +384,12 @@
if (config_space) begin
address_valid = address_r[1:0]==0;
end else if (io_space) begin
- address_valid = access_target_int[TARGET_IO];
+ address_valid = access_target_int[TARGET_IO_POSN];
end else if (mem_space) begin
- address_valid = access_target_int[TARGET_ENG] |
- access_target_int[TARGET_MEM] | access_target_int[TARGET_VMEM] |
- access_target_int[TARGET_PROM];
+ address_valid = access_target_int[TARGET_ENG_POSN] |
+ access_target_int[TARGET_MEM_POSN] |
+ access_target_int[TARGET_VMEM_POSN] |
+ access_target_int[TARGET_PROM_POSN];
end
end
@@ -697,8 +691,8 @@
always @(access_target_int or io_space or config_space) begin
access_target_int_pre = access_target_int;
- access_target_int_pre[TARGET_IO] = access_target_int[TARGET_IO] &&
io_space;
- access_target_int_pre[TARGET_CFG] = config_space;
+ access_target_int_pre[TARGET_IO_POSN] = access_target_int[TARGET_IO_POSN]
&& io_space;
+ access_target_int_pre[TARGET_CFG_POSN] = config_space;
end
// Store access target
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