2009/9/23 Hugh Fisher <[email protected]>:
> Andre Pouliot wrote:
>>
>> Yes all the vector ops will be emitted as scalar ops. The program do get
>> longer but scalar ops can be made shorter since we have less instruction
>> to
>> support.
>
> SIMD instructions are the same length as scalar instructions on any
> sensible CPU: see MIPS and PowerPC. Four scalar MADD instructions
> are going to be four times longer than the equivalent vector MADD.
>
> (Uh, you *are* intending to use fixed length instructions, right?
> Please tell me you're not thinking of variable length opcodes?)
>

Personnaly LIW is what i prefer : exposed every unit of the shader in
the instruction word. Then it became a software challenge to optimise
them.

One other solution is having word aligned instructions. So you could
have 32, 64, 128 bits instructions size.

If instruction code size matter, you could use such trick to reduce
the code size. Large instruction word is a must to have constant
embedded in the code and to save bandwith for the data.

If you could use 64 bits to squeeze an LIW instruction word that
enable the use of 3 units in the same time, you could have more
compact code than using typical 32 bits RISC instructions.

<...>
>
>> Those optimization were to improve 3D rendering and scientific processing
>> on
>> a general purpose processor. You don't have the same requirement and
>> workload as a GPU. Different problem and context require different
>> solution.
>
> It's exactly the same requirements and workload! 3D vertices have to be
> multipled by a 4x4 transform matrix. Doesn't matter whether it's on the
> CPU or GPU.
>

CPU don't use 1000th thread model at  the same time, that the main
difference. It's far easier to get 1Tflops with many thread on many
core (with very relaxed memory coherency model) than with 2 or 4
cores.
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