Timothy Normand Miller: >On Mon, Sep 21, 2009 at 9:41 PM, Hugh Fisher <[email protected]> wrote: >> Loads and stores are mostly of matrices (eg skinning), or materials >> and colors which are one or more 3/4-way RGB/RGBA vectors. > >Good argument for vector load instructions. I can totally buy that.
I see the point in vector load instructions, however, as a computer architect, I'm wondering if there is other ways to solve this. Mainly, cause I want to expose a simple ISA to the software developers ( Software developers here being the compilers and OpenGL driver developers ). What strikes me, and this isn't well though through yet, is that we might be able to "emulate", in lack of a better term, the performance gain of a vector load instruction by instead, increasing the cache line size from the naive 32 bit, to Y*(number of ALUs). This will have the effect that every time we make a request for address X, we will fetch the entire line. Although, it might not be the entire vector for a single thread, we can, by storing our data in interleaved fashion, make sure that it's the data for the threads that are to be scheduled on the cores in round. -- Life on the earth might be expensive, but it includes an annual free trip around the sun. Kenneth Østby http://langly.org
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