Ok, firstly my pcb is connected to the Intel board via PC/104-Plus connector. The PCI bus should communicate with the physical memory of the microcontroller. The microcontroller on my pcb is basically a CAN node and it receives/send data from/to CAN bus and transfers from/to CAN controller's buffer registers (mapped to the microcontroller's system memory). The CAN data has to be transferred to the Intel board and any data from Intel board has to be transferred to the CAN bus. The microcontroller on my pcb is Renesas V850E-DJ3.
Thanks! On 29 May 2011 21:23, Timothy Normand Miller <[email protected]> wrote: > Are you saying that you have a PCI bus directly connected to I/Os on a > microcontroller? If so, you would have to have a very fast CPU with > some incredibly precise timing in order to implement PCI signaling in > software. > > If you have an FPGA, then you can program a PCI controller in there, > and the OGP has one. But I can't give you a "snippet" of code. It's > much too complicated for that. > > On Sun, May 29, 2011 at 2:29 PM, Sanjeev Jamadhagni > <[email protected]> wrote: > > Hi, > > I have a problem. If you can help that would be of great help. > > I'm an undergraduate student. I'm implementing pci protocol for my > project > > in the uni. Aim: My pcb has to communicate with a pcb (contains Intel > > microcontroller + pci bridge) via pci protocol. In my pcb the > > microcontroller is Renesas (V850) and it doesn't have a pci controller. I > > did not use any standalone pci controllers in my pcb. I do not know if > it's > > possible to implement the pci config space registers in my > microcontroller. > > I do not have DeviceID and I suppose I can use any random number. Also, > the > > Intel pcb is not reprogrammable. All I have to do now is to implement > config > > space in my device and power on and check if the device is getting > detected. > > For this the Master (Intel pcb) has to read the config space and send > IDSEL > > signal. I'm going through the verilog code of the admin in this forum. > The > > verilog code given in Opencores forum is very complicated and I'm not > using > > wishbone. I want to map the device to memory space and did not understand > > the exact implementation of BAR. Can you please give a snippet of code > for > > implementing the config space? > > Thanks & regards > > S Jamadhagni > > _______________________________________________ > > Open-graphics mailing list > > [email protected] > > http://lists.duskglow.com/mailman/listinfo/open-graphics > > List service provided by Duskglow Consulting, LLC (www.duskglow.com) > > > > > > -- > Timothy Normand Miller > http://www.cse.ohio-state.edu/~millerti > Open Graphics Project >
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