Hi.

We are adding A & B.

A > B (without loss of generality).

A >= 1/2 & < 1

(I'm going to assume 7 bits of mantissa in my workings below, it's the same
for any number of bits).

So A >= 0x0.80 && A < 0x1.00

B can have any value < 0x1.00.  It can have the same exponent as A, in
which case it has the same range as A or it can have a smaller exponent,
and can be much smaller.  Only one bit to the right is important for
rounding, so the values of B that we are interested in are B >= 0x0.008 B <
0x1.000.

The bit of attached python enumerates all cases.

The short answer is that both cannot happen at the same time.

The reasoning is this.  If we have a carry out after the main addition we
must have at least one zero bit in the 8 bits below this carry bit.  This
will mean that when we add in the extra half for the rounding we won't get
another carry out.

Does that make sense?

I've assumed that A is normalized.

Mark M.


On 6 January 2013 20:16, Timothy Normand Miller <[email protected]> wrote:

> Here's an open question, and I'd like to see some kind of proof (formal or
> empirical) that addresses it.  Or maybe you can just look this up.  Surely
> we can come up with a single example that addresses this.  I'm just focused
> on writing code right now.
>
> When adding two FP numbers of the same sign, the sum can have a 1-bit
> carry to the left of the normalization bit of the greater mantissa.  In
> that case, we need to shift the sum right by one.
>
> But then we round.  And when we do that, carries can propagate such that
> we get an overflow AGAIN and have to shift right by one again.
>
> I'm pretty sure that both can happen, ultimately requiring two
> right-shifts (by zero or one, so they're cheap).  But am I right about that?
>
>
> --
> Timothy Normand Miller, PhD
> Assistant Professor of Computer Science, Binghamton University
> http://www.cs.binghamton.edu/~millerti/<http://www.cse.ohio-state.edu/~millerti>
> Open Graphics Project
>
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Attachment: fpadd.py
Description: Binary data

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