Moreover, the choice of multipliers is in some ways just a last-minute engineering decision. For this technology (whichever we're talking about at the time), what is the best implementation for a 33x33 multiplier? We now have two options that will work well for Xilinx FPGAs and some other similar devices. But some standard cell library may have a set of highly optimized macros for us to choose from, and we'd use that for an ASIC. What'll be nice with with many ASICs is that we can embed the multipliers right in the ALU, rather than having to route to a distant pre-compiled block out on the edge of the die, which really kills you on wire delays.
On Wed, Jan 23, 2013 at 1:42 PM, Chris Matrakidis <[email protected]>wrote: > Timothy, > > I'm perfectly fine with any license you want to use for the code I'm > helping you develop. It is your code, after all. > > In this specific instance, the formula is well known but is generally > only considered an option for recursive multiplication of very large > integers. Even there, switching to the lower overhead 4 multiplication > formula for the last iterations improves performance. Our case is > different in that the multiplier blocks are a limited resource, so the > additional complexity is definitely worth it. > > > Best Regards, > > Chris Matrakidis > _______________________________________________ > Open-graphics mailing list > [email protected] > http://lists.duskglow.com/mailman/listinfo/open-graphics > List service provided by Duskglow Consulting, LLC (www.duskglow.com) > -- Timothy Normand Miller, PhD Assistant Professor of Computer Science, Binghamton University http://www.cs.binghamton.edu/~millerti/ Open Graphics Project
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