For my Computer Architecture course, one of the assignments is to develop an ISA appropriate for the OpenShader ALU. Since students have completed that assignment, I have provided them with MY solution for the assignment. We can use this as a starting point for an ISA for our GPU.
You can find the document here: http://www.cs.binghamton.edu/~millerti/CS520-HW3-answers.pdf Although this is a GPU ALU, we're treating it like a multifunction ALU pipeline for a CPU. (At a certain level, they're really not all that different.) Thus, when I developed this ISA, I made choices that may be better for a CPU. There are also some drawbacks to its design (like missing PC-relative addressing), but we need to determine if those make any difference at all for a GPU. Also, I have some suggested fixes, but they're kludgy, and I'm not prepared to share them until my students have competed a later assignment. Speaking of the later assignment, I have also implemented this ISA in Verilog and put it through some rudimentary testing. This gave me the opportunity to fix a number of bugs and make a couple more optimizations. I'll share all of that once my students have completed that later assignment. I'll share it in the form of a tarball release on SourceForge. One thing I did that's somewhat superfluous is added support for hardware interlocks; this will be required neither for my students nor for the multi-threaded GPU (which is a barrel processor). But it was easy, and it does make functional testing of the ALU easier, because software interlocking is ugly. We'll make up a version number for that release. This is OpenShader as a primitive CPU. For another release, we can make it into a single-pipeline barrel processor, adding 16 thread contexts. Hopefully by that point, one of my students will have finished some important changes for his Masters project, and we can incorporate those into the ALU. And yet another release will see this turned from a stream processor into a stream multiprocessor, with four back-ends sharing the same fetch logic, giving us a complete 64-thread GPU module that can be synthesized into real designs. This first release (probably my mid-March) may be news-worthy. Hey, anyone care to write an assembler for this ISA? Do note that it is subject to change, and moreover, we want the ISA to be flexible so we can add and remove features. This is just one point in a continuum. -- Timothy Normand Miller, PhD Assistant Professor of Computer Science, Binghamton University http://www.cs.binghamton.edu/~millerti/ Open Graphics Project
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