Le 2013-03-17 21:20, Timothy Normand Miller a écrit :
<snip>
I'm looking here at the bit compactness, because
less bits means less toggles and less power draw.
Using a bit for each instruction to throw the register away : 1
bit/instruction
Using R0 : if you have, say, 64 registers, R0 will amount to 0,09
bits/address,
or if you use 3 addresses : 0,28 bits/instruction.
Drawback : you have to add 3 6-input OR gates to decode the R0
condition,
or create a custom register set where R0 is "hardwired".
However, all array generators need a regular, homogenous addressing
space.
FPGAs, ASICs etc. prefer and want memories where all the cells are
identical.
From a compactness point of view, it seems that an explicit opcode is
needed,
as "throwing away" the result is limited to only a handful of cases.
That's only an opinion and the best solution depends on each case.
YG
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