Le 2013-04-21 03:57, Timothy Normand Miller a écrit :
BTW, Ive changed some of the opcodes: http://www.cs.binghamton.edu/~millerti/ins-formats4.pdf [3]
"MUL instructions write top 32 bits to" A long time ago I played with the idea of using destr+1 as implicit destination for 2W instructions... But in your case, you don't seem to like the idea of a 2R2W register bank. Fine but now you have a heterogenous register file :-/ Lately i've done differently : mul and mulhi instructions, which select which part to put on the result bus. Consumption wise, if you emit/decode a consecutive pair of mul+mulhi, the operands and results remain the same (only the very last part is changed) so no big energy draw. But that is valid for an in-order CPU, not a barrell CPU where data are multiplexed from different threads... What do you think ? yg _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
