For fun and science, I and my students are porting Nyuzi to this Zynq 7000 FPGA prototyping board. We have a million and one things to do, so I was hoping some people with existing knowledge could save us some time here and there.
To get access to main DRAM on this chip, we need to use AXI protocol. What do we do to make the L2 cache in the FPGA fabric coherent with the caches in the ARM cores? Is it just particular messages? Or is it a different kind of bus? Do we have to maintain a directory? Thanks. -- Timothy Normand Miller, PhD Assistant Professor of Computer Science, Binghamton University http://www.cs.binghamton.edu/~millerti/ Open Graphics Project _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
