--- James Richard Tyrer wrote:
Using multiple SIMD processors controlled by microcode has the advantage 
that it is totally reconfigurable and you know how much hardware it will 
use.  It also should be scalable.  I have no doubt that a systolic array 
processor will run faster.  The questions are how much faster and how 
much hardware will it require.
--- end of quote ---
I think that this is a very good point. If our ASIC is large, even if it is 
larger
than any FPGA we have access to, we can just duplicate the SIMD units.
But enough talk of OGD1 and OGA. I am really excited about the Sun processor!
We can't use any of it on OGC, but we can fit 4 implementations of the FPU and
a bunch of spare processing into OGD1. Some time this break, I am going to
try to run one FPU on my Spartan 3E dev board, with a 500k gate FPGA on it.
It has only 10476 Logic Cells, and the FPU requires (IIRC) just over 13000, so
it will need to lose a few instructions :-)

Imagine having a bunch of smaller FPGAs, each one in charge of a part of the
computation, and each one is individually reprogrammable with a different set
of instructions.

--- continuation of quote ---
The number of hardware multipliers is always going to be a limiting
factor even if designing a custom ASIC because they take up a lot of
real estate on the chip and, therefore, consume a lot of power.
--- end of quote ---

I have been working on various units (mostly IDCT) for the ethervideo board,
and I can wholeheartedly agree that the number of hardware multipliers is the
large bottleneck in these superscalar designs. Even if SIMD is ignored, there
still needs to be a ton of multipliers running at the same time to keep 
throughput
high, since they are such a large part of any computation. I doubt that moving
to a custom ASIC architecture will help very much, if at all. With the execution
of an instruction as the main bandwidth limit, it is very important to have very
well designed routing as well.

nick
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