Hi Partners, Kindly let me know if you have any consultant for the following position.
* * *Please respond back with an updated resume and all inclusive rates to recrui...@burgeonits.com* * * Position: ASIC Verification and Validation Consultant Location: Folsom CA Duration: 6+ months JD: · Understand the requirement both (functional and non-functional) by going through the specifications and with inputs from Business Analysts, and participate in creating high level estimate as well as translating the same to system requirements · Participate in creating architecture document · Develop and review artifacts (code, documentation, test scripts) conduct reviews for self and peers, conduct unit tests and document unit tests for complex programs · Perform validation activities ( Functional, integration, system, user experience) based on the plans, identification and validation of defects found (including UAT) creation and reviewing of artifacts (test scripts, documentation, automation, setups) participate in performance testing · Participate in creating the implementation plan as per the project level quality plan and work on go live activities as per the implementation plan. · Respond to production issues and arrive at a solution with inputs from stakeholders, participate in estimating the effort needed to implement solution, test and implement the solution · Participate in handling customers as on site coordinators. Must have: · Hands on knowledge of System Verilog · Hands on working knowledge of methodologies like VMM, OVM, eRM · Strong hands-on experience on SOC projects. · Good experience in Full chip SOC and unit level validation. · Good knowledge of digital design concepts · Good knowledge of ASIC design flow · Hands on knowledge of complete ASIC Front-end verification flow – Verification planning to closure. · Good knowledge of Verilog/VHDL · Experience in defining verification plan · Experience in building re-usable verification environment · Understand the concept of random test generation and coverage · Experience on coverage points and SV assertion · Good team player and ability to work with stakeholders like RTL team, DFT team and Physical Design team · Good hands on knowledge of Gate level simulations (with back annotated delay values) · Good hands on knowledge of Planning and execution of IP level and fullchip verification Nice to have: · Experience on Intel SOCs · Experience on X86 * * Thanks & Regards *Raja* Burgeon IT Services LLC Ph: 302-220-4724 FAX: 302-355-1559 Email: recrui...@burgeonits.com Website: www.burgeonits.com -- You received this message because you are subscribed to the Google Groups "Open Source Erp & Crm" group. To unsubscribe from this group and stop receiving emails from it, send an email to open-source-erp-crm+unsubscr...@googlegroups.com. To post to this group, send email to open-source-erp-crm@googlegroups.com. Visit this group at http://groups.google.com/group/open-source-erp-crm. For more options, visit https://groups.google.com/groups/opt_out.
