Yes. This patch looks fine to me.
在 2010年9月1日 下午8:53，朱庆 <zqing1...@gmail.com>写道：
> I find a problem with this fix, _mm_extract_pi16 only exists in TARG_X8664,
> so the fix should add constraint to X8664.
> New patch is: (including some format adjusting), please help review it.
> Index: wgen_expr.cxx
> ===================================================================
> --- wgen_expr.cxx (revision 3333)
> +++ wgen_expr.cxx (working copy)
> @@ -3970,26 +3970,25 @@
>
> case GSBI_IX86_BUILTIN_VEC_EXT_V4HI:
> // add intrinsic for _mm_extract_pi16
>
> if (WN_operator(arg1) != OPR_INTCONST)
> - Fail_FmtAssertion ("selector must be an integer constant in the
> range 0..3");
> - switch (WN_const_val(arg1)){
> - case 0:
> - *iopc = INTRN_PEXTRW0;
> - break;
> - case 1:
> + Fail_FmtAssertion ("selector must be an integer constant in the
> range 0..3");
> + switch (WN_const_val(arg1)){
> + case 0:
> + *iopc = INTRN_PEXTRW0;
> + break;
> + case 1:
> *iopc = INTRN_PEXTRW1;
> - break;
> - case 2:
> - *iopc = INTRN_PEXTRW2;
> - break;
> - case 3:
> - *iopc = INTRN_PEXTRW3;
> - break;
> - default:
> - Fail_FmtAssertion ("selector must be an integer constant in the
> range 0..3" );
> - }
> - break;
> -
> - case GSBI_IX86_BUILTIN_VEC_EXT_V2DI:
> + break;
> + case 2:
> + *iopc = INTRN_PEXTRW2;
> + break;
> + case 3:
> + *iopc = INTRN_PEXTRW3;
> + break;
> + default:
> + Fail_FmtAssertion ("selector must be an integer constant in the
> range 0..3" );
> + }
> + break;
> + case GSBI_IX86_BUILTIN_VEC_EXT_V2DI:
> *iopc = INTRN_VEC_EXT_V2SI;
> break;
> case GSBI_IX86_BUILTIN_VEC_EXT_V2DF:
> @@ -9319,13 +9318,15 @@
> // if intrinsic equals _mm_extract_pi16,
>
> // the second param is fixed to const 0,1,2,3, so
> // there is no need to generate the second arg node.
> - if (i ==1 && (iopc == INTRN_PEXTRW0 ||
> - iopc == INTRN_PEXTRW1 ||
> - iopc == INTRN_PEXTRW2 ||
> - iopc == INTRN_PEXTRW3)) {
> - num_args = 1;
> - break;
> - }
> +#ifdef TARG_X8664
>
> + if (i ==1 && (iopc == INTRN_PEXTRW0 ||
> + iopc == INTRN_PEXTRW1 ||
> + iopc == INTRN_PEXTRW2 ||
> + iopc == INTRN_PEXTRW3)) {
> + num_args = 1;
> + break;
> + }
> +#endif
>
> arg_wn = WGEN_Expand_Expr (gs_tree_value (list));
>
> #ifdef KEY // bug 11286
>
> ------
> Thanks,
> zhuqing
>
> 在 2010年8月27日 上午7:08，Jian-Xin Lai <laij...@gmail.com>写道：
>
> It looks fine to me. Please commit it.
>>
>> 2010/8/25 朱庆 <zqing1...@gmail.com>
>>
>>> Hi, All
>>>
>>> Can gatekeeper help review this fix?
>>>
>>> This bug is about unsupported intrinsic, more detailed info please refer
>>> tohttps://bugs.open64.net/show_bug.cgi?id=602.
>>>
>>> The failure is due to unsupported intrinsic for _mm_extract_pi16.
>>> The fix is to add an entry for GSBI_IX86_BUILTIN_VEC_EXT_V4HI, and assign
>>> the correspond operator according to the second arg.
>>>
>>> Following is the fix:
>>>
>>> Index: osprey/wgen/wgen_expr.cxx
>>> ===================================================================
>>> --- osprey/wgen/wgen_expr.cxx (revision 3320)
>>> +++ osprey/wgen/wgen_expr.cxx (working copy)
>>> @@ -3967,7 +3967,29 @@
>>> case GSBI_IX86_BUILTIN_VEC_EXT_V4SI:
>>> *iopc = INTRN_VEC_EXT_V2SI;
>>> break;
>>> - case GSBI_IX86_BUILTIN_VEC_EXT_V2DI:
>>> + case GSBI_IX86_BUILTIN_VEC_EXT_V4HI:
>>> + //fix bug602, add intrinsic for _mm_extract_pi16
>>> + if (WN_operator(arg1) != OPR_INTCONST)
>>> + Fail_FmtAssertion ("selector must be an integer constant in the
>>> range 0..3");
>>> + switch (WN_const_val(arg1)){
>>> + case 0:
>>> + *iopc = INTRN_PEXTRW0;
>>> + break;
>>> + case 1:
>>> + *iopc = INTRN_PEXTRW1;
>>> + break;
>>> + case 2:
>>> + *iopc = INTRN_PEXTRW2;
>>> + break;
>>> + case 3:
>>> + *iopc = INTRN_PEXTRW3;
>>> + break;
>>> + default:
>>> + Fail_FmtAssertion ("selector must be an integer constant in the
>>> range 0..3" );
>>> + }
>>> + break;
>>> +
>>> + case GSBI_IX86_BUILTIN_VEC_EXT_V2DI:
>>> *iopc = INTRN_VEC_EXT_V2SI;
>>> break;
>>> case GSBI_IX86_BUILTIN_VEC_EXT_V2DF:
>>> @@ -9294,7 +9316,18 @@
>>> for (i = 0, list = gs_tree_operand (exp, 1);
>>> list;
>>> i++, list = gs_tree_chain (list)) {
>>> - arg_wn = WGEN_Expand_Expr (gs_tree_value (list));
>>> + //fix bug602, if intrinsic equals _mm_extract_pi16,
>>> + //the second param is fixed to const 0,1,2,3, so
>>> + //there is no need to generate the second arg node.
>>> + if (i ==1 && (iopc == INTRN_PEXTRW0 ||
>>> + iopc == INTRN_PEXTRW1 ||
>>> + iopc == INTRN_PEXTRW2 ||
>>> + iopc == INTRN_PEXTRW3)) {
>>> + num_args = 1;
>>> + break;
>>> + }
>>> + arg_wn = WGEN_Expand_Expr (gs_tree_value (list));
>>> +
>>> #ifdef KEY // bug 11286
>>> if (i == 1 && TARGET_64BIT &&
>>> (gs_decl_function_code(func) == GSBI_BUILT_IN_POWI ||
>>>
>>> Best Regards,
>>> Zhu Qing
>>>
>>> ------------------------------------------------------------------------------
>>> Sell apps to millions through the Intel(R) Atom(Tm) Developer Program
>>> Be part of this innovative community and reach millions of netbook users
>>> worldwide. Take advantage of special opportunities to increase revenue
>>> and
>>> speed time-to-market. Join now, and jumpstart your future.
>>> http://p.sf.net/sfu/intel-atom-d2d
>>> _______________________________________________
>>> Open64-devel mailing list
>>> Open64-devel@lists.sourceforge.net
>>> https://lists.sourceforge.net/lists/listinfo/open64-devel
>>>
>>>
>>
>>
>> --
>> Regards,
>> Lai Jian-Xin
>>
>
>
--
Regards,
Lai Jian-Xin
------------------------------------------------------------------------------
This SF.net Dev2Dev email is sponsored by:
Show off your parallel programming skills.
Enter the Intel(R) Threading Challenge 2010.
http://p.sf.net/sfu/intel-thread-sfd
_______________________________________________
Open64-devel mailing list
Open64-devel@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/open64-devel
