If any researchers are interested in GPGPU ping me. We have a huge
amount of research topics and unpublished work someone could turn into a
paper.
--- Begin Message ---
[Apologies if you receive multiple copies of this CFP]
First International Workshop on
Accelerators Architectures for the Masses (WACy 2011)
held in conjunction with 25th Int'l. Conference on Supercomputing,
(ICS 2011)
June 4th 2011
We encourage the submission of short papers (approximately ~6 pages).
Submission deadline : April 15th 11:59pm PST
The top 1 to 2 papers will be selected for publication in IEEE CAL
(http://www.computer.org/portal/web/cal/home) if they match the scope
of CAL.
Workshop objectives
-------------------
This workshop envisions a future in which the multicore chip includes
specialized compute accelerator cores that take care of the bulk of
the computation. These heterogeneous manycore chips that integrate
novel domain specific hardware units with general-purpose CPUs promise
high levels of performance and energy-efficiency. At this time, there
is a critical need for research to enable widespread use of manycore
accelerators like GP-GPUs across a wide variety of mainstream
applications and programming paradigms
This workshop seeks to bring together computer architects, software
researchers, and application developers for a discussion on the
potential and challenges for the accelerator vision. We would like to
understand the architecture and design of these manycore chips and
figure out what needs acceleration. We would also like to study the
the types of applications and the programming constructs that will
help us harness these diverse types of cores. We hope to develop a
well-integrated program that addresses includes presentations on the
systems architecture, software runtime, OS support, and applications
for accelerators.
Topics of Interest
------------------
- Novel accelerator and GP-GPU architectures.
- How do we integrate GPUs, accelerators and CPUs for general
purpose computing?
- Memory system and Interconnects for GPUs and accelerators.
- Accelerator-awareness in the general-purpose processor?
- Runtime systems and programming environments for heterogeneous
architectures
- OS resource management and scheduling
- Characterizing energy efficiency of accelerator-based computing
- Profiling infrastructure to identify acceleratable parts of the
application
- Analytical modeling
- Application case studies
Organizers
----------
Arrvindh Shriraman, Simon Fraser University
Tor Aamodt, University of British Columbia
Program Committee
-----------------
Rajeev Balasubromanian, University of Utah
James Balfour, NVIDIA Research
Mike O'Connor, AMD Research
Ali Bakhoda, UBC
Michael C. Huang, University of Rochester
Hyesoon Kim, Georgia Tech
Natalie Enright Jerger, University of Toronto
Wilson Fung, UBC
David Kaeli,North Eastern University
Paul Lalonde, Intel Labs
Steve Lumetta, University of Illionois
P. Sadayappan, Ohio State University
Michael Shebanow, Nvidia Research
Mattan Erez , UT Austin
Greg Steffan, University of Toronto
Michael Schulte, AMD Research
Paper Submission
----------------
To ensure a proactive workshop we encourage the submission of short
papers (~ 6 pages, 2 column ACM SIG format). Accepted papers will be
available to participants at the meeting and will also be posted on
our workshop website. However, there will be no archival proceedings
to facilitate future submission to more formal venues.
Submission website:
https://www.easychair.org/conferences/?conf=wacy2011
--
You received this message because you are subscribed to the Google Groups
"GPGPU-Sim" group.
To post to this group, send email to gpgpu-...@googlegroups.com.
To unsubscribe from this group, send email to
gpgpu-sim+unsubscr...@googlegroups.com.
For more options, visit this group at
http://groups.google.com/group/gpgpu-sim?hl=en.
--- End Message ---
------------------------------------------------------------------------------
Enable your software for Intel(R) Active Management Technology to meet the
growing manageability and security demands of your customers. Businesses
are taking advantage of Intel(R) vPro (TM) technology - will your software
be a part of the solution? Download the Intel(R) Manageability Checker
today! http://p.sf.net/sfu/intel-dev2devmar
_______________________________________________
Open64-devel mailing list
Open64-devel@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/open64-devel
