Could a gatekeeper please review the attached patch? Most changes are
in the cg. The proposed log message is:
Implement a frame-pointer optimization for the x86 target.
When there is no dynamic allocation of stack in the PU, it is not
necessary to use register %rbp as the frame pointer. In this case
the .eh_frame section needs to describe the location of the registers
needed to support unwinding for exception handling.
Thanks,
-David Coakley / AMD Open Source Compiler Engineering
Index: osprey/be/be/driver.cxx
===================================================================
--- osprey/be/be/driver.cxx (revision 3583)
+++ osprey/be/be/driver.cxx (working copy)
@@ -1967,7 +1967,7 @@
Pu_Table [ST_pu (St_Table [PU_Info_proc_sym (current_pu)])];
// C++ PU having exception regions, or with -g
- if ((PU_cxx_lang (func) && PU_has_region (func)) || Debug_Level > 0
+ if (Debug_Level > 0
#ifdef KEY
|| PU_has_goto_outer_block(func)
#endif
Index: osprey/be/cg/cgdwarf.cxx
===================================================================
--- osprey/be/cg/cgdwarf.cxx (revision 3583)
+++ osprey/be/cg/cgdwarf.cxx (working copy)
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2009 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (C) 2009-2010 Advanced Micro Devices, Inc. All Rights Reserved.
*/
/*
@@ -2438,15 +2438,25 @@
end_offset,
low_pc, high_pc);
#else
- Dwarf_Unsigned pushbp_entry = Cg_Dwarf_Symtab_Entry(CGD_LABIDX,
- eh_pushbp_label[0],
- scn_index);
- Dwarf_Unsigned movespbp_entry = Cg_Dwarf_Symtab_Entry(CGD_LABIDX,
- eh_movespbp_label[0],
- scn_index);
- Dwarf_Unsigned adjustsp_entry = Cg_Dwarf_Symtab_Entry(CGD_LABIDX,
- eh_adjustsp_label[0],
- scn_index);
+ Dwarf_Unsigned pushbp_entry;
+ Dwarf_Unsigned movespbp_entry;
+ if (Current_PU_Stack_Model != SMODEL_SMALL)
+ {
+ pushbp_entry = Cg_Dwarf_Symtab_Entry(CGD_LABIDX,
+ eh_pushbp_label[0],
+ scn_index);
+ movespbp_entry = Cg_Dwarf_Symtab_Entry(CGD_LABIDX,
+ eh_movespbp_label[0],
+ scn_index);
+ }
+ Dwarf_Unsigned adjustsp_entry;
+ if (eh_adjustsp_label[0] != 0)
+ adjustsp_entry = Cg_Dwarf_Symtab_Entry(CGD_LABIDX,
+ eh_adjustsp_label[0],
+ scn_index);
+ else
+ adjustsp_entry = begin_entry;
+
Dwarf_Unsigned callee_saved_reg;
INT num_callee_saved_regs;
if (num_callee_saved_regs = Cgdwarf_Num_Callee_Saved_Regs())
@@ -2508,12 +2518,15 @@
end_entry = Cg_Dwarf_Symtab_Entry(CGD_LABIDX,
last_bb_labels[pu_entry],
scn_index);
- pushbp_entry = Cg_Dwarf_Symtab_Entry(CGD_LABIDX,
+ if (Current_PU_Stack_Model != SMODEL_SMALL)
+ {
+ pushbp_entry = Cg_Dwarf_Symtab_Entry(CGD_LABIDX,
eh_pushbp_label[pu_entry],
scn_index);
- movespbp_entry = Cg_Dwarf_Symtab_Entry(CGD_LABIDX,
+ movespbp_entry = Cg_Dwarf_Symtab_Entry(CGD_LABIDX,
eh_movespbp_label[pu_entry],
scn_index);
+ }
adjustsp_entry = Cg_Dwarf_Symtab_Entry(CGD_LABIDX,
eh_adjustsp_label[pu_entry],
scn_index);
Index: osprey/be/cg/x8664/cgdwarf_targ.cxx
===================================================================
--- osprey/be/cg/x8664/cgdwarf_targ.cxx (revision 3583)
+++ osprey/be/cg/x8664/cgdwarf_targ.cxx (working copy)
@@ -1,4 +1,8 @@
/*
+ * Copyright (C) 2010-2011 Advanced Micro Devices, Inc. All Rights Reserved.
+ */
+
+/*
* Copyright (C) 2007. PathScale, LLC. All Rights Reserved.
*/
/*
@@ -100,37 +104,68 @@
INT low_pc,
INT high_pc)
{
+ BOOL stack_used = FALSE;
Dwarf_Error dw_error;
Dwarf_P_Fde fde;
if ( ! CG_emit_unwind_info) return NULL;
+ {
+ OP *op;
+ for (op = BB_first_op(firstbb); op != NULL; op = OP_next(op))
+ {
+ if (OP_result(op, 0) == SP_TN ||
+ OP_code(op) == TOP_pushq || OP_code(op) == TOP_pushl)
+ {
+ stack_used = TRUE;
+ break;
+ }
+ }
+ }
+
fde = dwarf_new_fde (dw_dbg, &dw_error);
- // Generate FDE instructions
- dwarf_add_fde_inst (fde, DW_CFA_advance_loc4,
+ if (Current_PU_Stack_Model != SMODEL_SMALL)
+ {
+ // Generate FDE instructions
+ dwarf_add_fde_inst (fde, DW_CFA_advance_loc4,
begin_label, movespbp_label, &dw_error);
- dwarf_add_fde_inst (fde, DW_CFA_def_cfa_offset,
+ dwarf_add_fde_inst (fde, DW_CFA_def_cfa_offset,
Is_Target_64bit() ? 0x10 : 0x8,
0x0, &dw_error);
- dwarf_add_fde_inst (fde, DW_CFA_offset, Is_Target_64bit() ? 0x6 : 0x5,
+ dwarf_add_fde_inst (fde, DW_CFA_offset, Is_Target_64bit() ? 0x6 : 0x5,
0x2, &dw_error);
- dwarf_add_fde_inst (fde, DW_CFA_advance_loc4,
+ dwarf_add_fde_inst (fde, DW_CFA_advance_loc4,
movespbp_label, adjustsp_label, &dw_error);
- dwarf_add_fde_inst (fde, DW_CFA_def_cfa_register,
+ dwarf_add_fde_inst (fde, DW_CFA_def_cfa_register,
Is_Target_64bit() ? 0x6 : 0x5, 0x0, &dw_error);
- if (Cgdwarf_Num_Callee_Saved_Regs()) {
+ } else {
+ dwarf_add_fde_inst (fde, DW_CFA_advance_loc4,
+ begin_label, adjustsp_label, &dw_error);
+ if (stack_used && Frame_Len != 0)
+ dwarf_add_fde_inst (fde, DW_CFA_def_cfa_offset,
+ Frame_Len + (Push_Pop_Int_Saved_Regs() + 1)*(Is_Target_64bit()?8:4),
+ 0x0, &dw_error);
+ else
+ dwarf_add_fde_inst (fde, DW_CFA_def_cfa_offset,
+ Is_Target_64bit()?8:4,
+ 0x0, &dw_error);
+ }
+ if (stack_used && Cgdwarf_Num_Callee_Saved_Regs() != 0) {
INT num = Cgdwarf_Num_Callee_Saved_Regs();
dwarf_add_fde_inst (fde, DW_CFA_advance_loc4,
adjustsp_label,
- callee_saved_reg, &dw_error);
+ callee_saved_reg, &dw_error);
for (INT i = num - 1; i >= 0; i --) {
TN* tn = Cgdwarf_Nth_Callee_Saved_Reg(i);
ST* sym = Cgdwarf_Nth_Callee_Saved_Reg_Location(i);
INT n = Is_Target_64bit() ? 16 : 8;
// data alignment factor
INT d_align = Is_Target_64bit() ? 8 : 4;
+ INT64 d_frame_len;
mUINT8 reg_id = REGISTER_machine_id (TN_register_class(tn), TN_register(tn));
+
+ d_frame_len = Frame_Len/d_align + (Push_Pop_Int_Saved_Regs() + 1);
// If we need the DWARF register id's for all registers, we need a
// general register mapping from REGISTER_machine_id to DWARF register
// id. But the following suffices for this case,
@@ -144,11 +179,22 @@
reg_id = 6;
else if (reg_id == 4) // %edi
reg_id = 7;
+ else if (reg_id == 2) // %ebp
+ reg_id = 5;
+ } else {
+ if (reg_id == 2) //%rbp
+ reg_id = 6;
}
if (reg_id == 1) reg_id = 3; // %rbx
- dwarf_add_fde_inst (fde, DW_CFA_offset, reg_id,
- ((ST_base(sym) == FP_Sym ? -1 : 1)*ST_ofst(sym)+n)/d_align,
+ if (Current_PU_Stack_Model != SMODEL_SMALL)
+ dwarf_add_fde_inst (fde, DW_CFA_offset, reg_id,
+ (((ST_base(sym) == FP_Sym) ? -1 : 1)*ST_ofst(sym)+n)/d_align,
&dw_error);
+ else
+ dwarf_add_fde_inst (fde, DW_CFA_offset, reg_id,
+ d_frame_len - (ST_ofst(sym))/d_align,
+ &dw_error);
+
}
}
Index: osprey/be/cg/gra_mon/gra_spill.cxx
===================================================================
--- osprey/be/cg/gra_mon/gra_spill.cxx (revision 3583)
+++ osprey/be/cg/gra_mon/gra_spill.cxx (working copy)
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2008-2009 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (C) 2008-2010 Advanced Micro Devices, Inc. All Rights Reserved.
*/
/*
@@ -1314,6 +1314,7 @@
#ifdef TARG_X8664
TN* orig_tn = lrange->Original_TN();
if (CG_push_pop_int_saved_regs && ! Gen_Frame_Pointer &&
+ ! (PU_cxx_lang (Get_Current_PU()) && PU_has_region (Get_Current_PU())) &&
! TN_is_float(orig_tn) && TN_is_save_reg(orig_tn)) {
// put saved location info in Saved_Callee_Saved_Regs for dwarf generation
SAVE_REG_LOC sr;
Index: osprey/be/cg/cg.cxx
===================================================================
--- osprey/be/cg/cg.cxx (revision 3583)
+++ osprey/be/cg/cg.cxx (working copy)
@@ -753,7 +753,8 @@
// Cannot enable emit_unwind_info if Force_Frame_Pointer is not set
// Need this flag set for C++ exceptions and for -g
if (!CG_emit_unwind_info_Set)
- CG_emit_unwind_info = Force_Frame_Pointer;
+ CG_emit_unwind_info = (Force_Frame_Pointer
+ || (PU_cxx_lang (Get_Current_PU()) && PU_has_region (Get_Current_PU())));
// Don't eliminate prologue OPs in main because they guide cgemit.cxx on
// where to insert OPs to set up the control registers. Bug 8141.
------------------------------------------------------------------------------
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