The attached patch adds support for the SSE 4.1 instructions used to
read and write XMM registers and cleans up some issues where support
had already been partially added.
Could a gatekeeper please review it? Thanks,
-David Coakley / AMD Open Source Compiler Engineering
Index: osprey/be/cg/x8664/expand.cxx
===================================================================
--- osprey/be/cg/x8664/expand.cxx (revision 3664)
+++ osprey/be/cg/x8664/expand.cxx (working copy)
@@ -7550,6 +7550,24 @@
op1 = Gen_Literal_TN (3, 4);
Build_OP( TOP_pextrw, result, op0, op1, ops );
break;
+ case INTRN_PEXTRB:
+ Build_OP( TOP_extr128v8, result, op0, op1, ops);
+ break;
+ case INTRN_PEXTRW:
+ Build_OP( TOP_extr128v16, result, op0, op1, ops);
+ break;
+ case INTRN_PEXTRD:
+ Build_OP( TOP_extr128v32, result, op0, op1, ops);
+ break;
+ case INTRN_PEXTRQ:
+ Build_OP( TOP_extr128v64, result, op0, op1, ops);
+ break;
+ case INTRN_EXTRPS:
+ Build_OP( TOP_fextr128v32, result, op0, op1, ops);
+ break;
+ case INTRN_EXTRPD:
+ FmtAssert(FALSE, ("TODO: support fextr128v64"));
+ break;
case INTRN_PINSRW0:
Is_True (op2 == NULL, ("Imm operand should be null"));
op2 = Gen_Literal_TN (0, 4);
@@ -7570,6 +7588,24 @@
op2 = Gen_Literal_TN (3, 4);
Build_OP( TOP_pinsrw, result, op1, op2, ops );
break;
+ case INTRN_PINSRB:
+ Build_OP( TOP_insr128v8, result, op0, op1, op2, ops);
+ break;
+ case INTRN_PINSRW:
+ Build_OP( TOP_insr128v16, result, op0, op1, op2, ops);
+ break;
+ case INTRN_PINSRD:
+ Build_OP( TOP_insr128v32, result, op0, op1, op2, ops);
+ break;
+ case INTRN_PINSRQ:
+ Build_OP( TOP_insr128v64, result, op0, op1, op2, ops);
+ break;
+ case INTRN_INSRPS:
+ Build_OP( TOP_finsr128v32, result, op0, op1, op2, ops);
+ break;
+ case INTRN_INSRPD:
+ FmtAssert(FALSE, ("TODO: support finsr128v64"));
+ break;
case INTRN_PMOVMSKB:
Build_OP( TOP_pmovmskb, result, op0, ops );
break;
Index: osprey/be/cg/x8664/cgemit_targ.cxx
===================================================================
--- osprey/be/cg/x8664/cgemit_targ.cxx (revision 3664)
+++ osprey/be/cg/x8664/cgemit_targ.cxx (working copy)
@@ -1139,6 +1139,7 @@
OP_Name[TOP_extrx128v16] = "pextrw";
OP_Name[TOP_extrxx128v16] = "pextrw";
OP_Name[TOP_extrxxx128v16] = "pextrw";
+ OP_Name[TOP_extr128v32] = "pextrd";
OP_Name[TOP_extrx128v32] = "pextrd";
OP_Name[TOP_extrxx128v32] = "pextrd";
OP_Name[TOP_extrxxx128v32] = "pextrd";
Index: osprey/be/cg/whirl2ops.cxx
===================================================================
--- osprey/be/cg/whirl2ops.cxx (revision 3664)
+++ osprey/be/cg/whirl2ops.cxx (working copy)
@@ -3730,6 +3730,12 @@
// SSSE3
case INTRN_PALIGNR:
// SSE4.1
+ case INTRN_PINSRB:
+ case INTRN_PINSRW:
+ case INTRN_PINSRD:
+ case INTRN_PINSRQ:
+ case INTRN_INSRPS:
+ case INTRN_INSRPD:
case INTRN_BLENDPD:
case INTRN_BLENDPS:
case INTRN_DPPD:
@@ -3820,6 +3826,12 @@
case INTRN_PSHUFW:
case INTRN_PSHUFLW:
case INTRN_PSHUFHW:
+ case INTRN_PEXTRB:
+ case INTRN_PEXTRW:
+ case INTRN_PEXTRD:
+ case INTRN_PEXTRQ:
+ case INTRN_EXTRPS:
+ case INTRN_EXTRPD:
// AES
case INTRN_AESKEYGENASSIST128:
// XOP
Index: osprey/common/targ_info/isa/x8664/isa_print.cxx
===================================================================
--- osprey/common/targ_info/isa/x8664/isa_print.cxx (revision 3664)
+++ osprey/common/targ_info/isa/x8664/isa_print.cxx (working copy)
@@ -1412,11 +1412,6 @@
TOP_fblend128v64,
TOP_fdp128v32,
TOP_fdp128v64,
- TOP_extr128v8,
- TOP_extr128v16,
- TOP_extr128v32,
- TOP_extr128v64,
- TOP_fextr128v32,
TOP_insr128v8,
TOP_insr128v16,
TOP_insr128v32,
@@ -1598,6 +1593,12 @@
Operand(0);
Result(0);
Instruction_Print_Group( vropop,
+ /* SSE 4.1 instruction */
+ TOP_extr128v8,
+ TOP_extr128v16,
+ TOP_extr128v32,
+ TOP_extr128v64,
+ TOP_fextr128v32,
/* AES instruction */
TOP_aeskeygenassist,
/* XOP instruction */
@@ -1997,6 +1998,12 @@
Operand(0);
Result(0);
Instruction_Print_Group( vrmemop,
+ /* SSE 4.1 instruction */
+ TOP_extrx128v8,
+ TOP_extrx128v16,
+ TOP_extrx128v32,
+ TOP_extrx128v64,
+ TOP_fextrx128v32,
/* XOP instruction */
TOP_vprotbx,
TOP_vprotdx,
@@ -2219,6 +2226,12 @@
Operand(2);
Result(0);
Instruction_Print_Group( vrmemindexop,
+ /* SSE 4.1 instruction */
+ TOP_extrxx128v8,
+ TOP_extrxx128v16,
+ TOP_extrxx128v32,
+ TOP_extrxx128v64,
+ TOP_fextrxx128v32,
/* XOP instruction */
TOP_vprotbxx,
TOP_vprotdxx,
@@ -2439,6 +2452,12 @@
Operand(1);
Result(0);
Instruction_Print_Group( vropmemindex,
+ /* SSE 4.1 instruction */
+ TOP_extrxxx128v8,
+ TOP_extrxxx128v16,
+ TOP_extrxxx128v32,
+ TOP_extrxxx128v64,
+ TOP_fextrxxx128v32,
/* XOP instruction */
TOP_vprotbxxx,
TOP_vprotdxxx,
Index: osprey/common/targ_info/isa/x8664/isa_properties.cxx
===================================================================
--- osprey/common/targ_info/isa/x8664/isa_properties.cxx (revision 3664)
+++ osprey/common/targ_info/isa/x8664/isa_properties.cxx (working copy)
@@ -12178,22 +12178,6 @@
TOP_insrx128v64,
TOP_insrxx128v64,
TOP_insrxxx128v64,
- TOP_extr128v8,
- TOP_extrx128v8,
- TOP_extrxx128v8,
- TOP_extrxxx128v8,
- TOP_extr128v16,
- TOP_extrx128v16,
- TOP_extrxx128v16,
- TOP_extrxxx128v16,
- TOP_extr128v32,
- TOP_extrx128v32,
- TOP_extrxx128v32,
- TOP_extrxxx128v32,
- TOP_extr128v64,
- TOP_extrx128v64,
- TOP_extrxx128v64,
- TOP_extrxxx128v64,
TOP_mpsadbw,
TOP_mpsadbwx,
TOP_mpsadbwxx,
@@ -14417,10 +14401,6 @@
TOP_finsrx128v32,
TOP_finsrxx128v32,
TOP_finsrxxx128v32,
- TOP_fextr128v32,
- TOP_fextrx128v32,
- TOP_fextrxx128v32,
- TOP_fextrxxx128v32,
/* SSE4.2 instructions */
TOP_crc32b,
TOP_crc32bx,
Index: osprey/common/com/intrn_entry.def
===================================================================
--- osprey/common/com/intrn_entry.def (revision 3664)
+++ osprey/common/com/intrn_entry.def (working copy)
@@ -3834,6 +3834,54 @@
DEF_INTRN_ENTRY(INTRN_PINSRW3, "PINSRW3", BYVAL, PURE, NO_SIDEEFFECTS,
DOES_RETURN, NOT_ACTUAL, CGINTRINSIC, NOT_SLAVE,
IRETURN_M8I2, "PINSRW3", NULL, NULL)
+/* PEXTRB */
+DEF_INTRN_ENTRY(INTRN_PEXTRB, "PEXTRB", BYVAL, PURE, NO_SIDEEFFECTS,
+ DOES_RETURN, NOT_ACTUAL, CGINTRINSIC, NOT_SLAVE,
+ IRETURN_I1, "PEXTRB", NULL, NULL)
+/* PEXTRW */
+DEF_INTRN_ENTRY(INTRN_PEXTRW, "PEXTRW", BYVAL, PURE, NO_SIDEEFFECTS,
+ DOES_RETURN, NOT_ACTUAL, CGINTRINSIC, NOT_SLAVE,
+ IRETURN_I2, "PEXTRW", NULL, NULL)
+/* PEXTRD */
+DEF_INTRN_ENTRY(INTRN_PEXTRD, "PEXTRD", BYVAL, PURE, NO_SIDEEFFECTS,
+ DOES_RETURN, NOT_ACTUAL, CGINTRINSIC, NOT_SLAVE,
+ IRETURN_I4, "PEXTRD", NULL, NULL)
+/* PEXTRQ */
+DEF_INTRN_ENTRY(INTRN_PEXTRQ, "PEXTRQ", BYVAL, PURE, NO_SIDEEFFECTS,
+ DOES_RETURN, NOT_ACTUAL, CGINTRINSIC, NOT_SLAVE,
+ IRETURN_I8, "PEXTRQ", NULL, NULL)
+/* EXTRPS */
+DEF_INTRN_ENTRY(INTRN_EXTRPS, "EXTRPS", BYVAL, PURE, NO_SIDEEFFECTS,
+ DOES_RETURN, NOT_ACTUAL, CGINTRINSIC, NOT_SLAVE,
+ IRETURN_F4, "EXTRPS", NULL, NULL)
+/* EXTRPD */
+DEF_INTRN_ENTRY(INTRN_EXTRPD, "EXTRPD", BYVAL, PURE, NO_SIDEEFFECTS,
+ DOES_RETURN, NOT_ACTUAL, CGINTRINSIC, NOT_SLAVE,
+ IRETURN_F8, "EXTRPD", NULL, NULL)
+/* PINSRB */
+DEF_INTRN_ENTRY(INTRN_PINSRB, "PINSRB", BYVAL, PURE, NO_SIDEEFFECTS,
+ DOES_RETURN, NOT_ACTUAL, CGINTRINSIC, NOT_SLAVE,
+ IRETURN_V16I1, "PINSRB", NULL, NULL)
+/* PINSRW */
+DEF_INTRN_ENTRY(INTRN_PINSRW, "PINSRW", BYVAL, PURE, NO_SIDEEFFECTS,
+ DOES_RETURN, NOT_ACTUAL, CGINTRINSIC, NOT_SLAVE,
+ IRETURN_V16I2, "PINSRW", NULL, NULL)
+/* PINSRD */
+DEF_INTRN_ENTRY(INTRN_PINSRD, "PINSRD", BYVAL, PURE, NO_SIDEEFFECTS,
+ DOES_RETURN, NOT_ACTUAL, CGINTRINSIC, NOT_SLAVE,
+ IRETURN_V16I4, "PINSRD", NULL, NULL)
+/* PINSRQ */
+DEF_INTRN_ENTRY(INTRN_PINSRQ, "PINSRQ", BYVAL, PURE, NO_SIDEEFFECTS,
+ DOES_RETURN, NOT_ACTUAL, CGINTRINSIC, NOT_SLAVE,
+ IRETURN_V16I8, "PINSRQ", NULL, NULL)
+/* INSRPS */
+DEF_INTRN_ENTRY(INTRN_INSRPS, "INSRPS", BYVAL, PURE, NO_SIDEEFFECTS,
+ DOES_RETURN, NOT_ACTUAL, CGINTRINSIC, NOT_SLAVE,
+ IRETURN_V16F4, "INSRPS", NULL, NULL)
+/* INSRPD */
+DEF_INTRN_ENTRY(INTRN_INSRPD, "INSRPD", BYVAL, PURE, NO_SIDEEFFECTS,
+ DOES_RETURN, NOT_ACTUAL, CGINTRINSIC, NOT_SLAVE,
+ IRETURN_V16F8, "INSRPD", NULL, NULL)
/* PMOVMSKB */
DEF_INTRN_ENTRY(INTRN_PMOVMSKB, "PMOVMSKB", BYVAL, PURE, NO_SIDEEFFECTS,
DOES_RETURN, NOT_ACTUAL, CGINTRINSIC, NOT_SLAVE,
@@ -7683,6 +7731,16 @@
DOES_RETURN, ACTUAL, NOT_CGINTRINSIC, NOT_SLAVE,
IRETURN_SZT, NULL, NULL, "dummy_name")
+/* SWITCH_RETURN */
+DEF_INTRN_ENTRY(INTRN_SWITCH_RETURN, "SWITCH_RETURN", NOT_BYVAL, PURE, NO_SIDEEFFECTS,
+ DOES_RETURN, NOT_ACTUAL, NOT_CGINTRINSIC, NOT_SLAVE,
+ IRETURN_UNKNOWN, "__switch_return", "switch_return", "__switch_return")
+
+/* Vector SWITCH_RETURN */
+DEF_INTRN_ENTRY(INTRN_VSWITCH_RETURN, "VSWITCH_RETURN", BYVAL, PURE, NO_SIDEEFFECTS,
+ DOES_RETURN, NOT_ACTUAL, NOT_CGINTRINSIC, NOT_SLAVE,
+ IRETURN_UNKNOWN, "__vswitch_return", "vswitch_return", "__vswitch_return")
+
/* END of DEF_INTRN_ENTRY */
#if defined (DEF_INTRN_ENTRY)
------------------------------------------------------------------------------
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