Index: osprey/be/cg/x8664/expand.cxx
===================================================================
--- osprey/be/cg/x8664/expand.cxx	(revision 1439)
+++ osprey/be/cg/x8664/expand.cxx	(working copy)
@@ -8872,8 +8872,8 @@
     Build_OP(TOP_vmovaps, result, op0, ops );
     break;
    case INTRN_I2POPCNT:
-    if ( Is_Target_SSE42() || Is_Target_SSE4a() ) {
-      // SSE4.2(Intel) and SSE4a(AMD) supports popcnt
+    if ( Is_Target_SSE42() || Is_Target_Barcelona()) {
+      // popcnt available since Barcelona and Nehalem
       Build_OP(TOP_popcnt16, result, op0, ops);
     }
     else {
@@ -8881,8 +8881,8 @@
     }
     break;
    case INTRN_I4POPCNT:
-    if ( Is_Target_SSE42() || Is_Target_SSE4a() ) {
-      // SSE4.2(Intel) and SSE4a(AMD) supports popcnt
+    if ( Is_Target_SSE42() || Is_Target_Barcelona()) {
+      // popcnt available since Barcelona and Nehalem
       Build_OP(TOP_popcnt32, result, op0, ops);
     }
     else {
@@ -8891,8 +8891,8 @@
     break;
    case INTRN_I8POPCNT:
     if ( Is_Target_64bit() && 
-         ( Is_Target_SSE42() || Is_Target_SSE4a() ) ) {
-      // SSE4.2(Intel) and SSE4a(AMD) supports popcnt
+         ( Is_Target_SSE42() || Is_Target_Barcelona()) ) {
+      // popcnt available since Barcelona and Nehalem
       Build_OP(TOP_popcnt64, result, op0, ops);
     }
     else {
Index: osprey/be/com/wn_lower.cxx
===================================================================
--- osprey/be/com/wn_lower.cxx	(revision 1439)
+++ osprey/be/com/wn_lower.cxx	(working copy)
@@ -5911,13 +5911,16 @@
     }
     if( ( (INTRINSIC)WN_intrinsic(tree) == INTRN_I2POPCNT ||
           (INTRINSIC)WN_intrinsic(tree) == INTRN_I4POPCNT ) &&
-        ( Is_Target_SSE42() || Is_Target_SSE4a() ) ) {
-      // SSE4.2(Intel) and SSE4a(AMD) supports I2 and I4 popcnt
+        ( Is_Target_SSE42() || Is_Target_Barcelona() 
+          || Is_Target_Orochi()) ) {
+      // Support for POPCNT is available with AMD
+      //  Barcelona onwards and Intel Nehalem onwards
       break;
     }
     if( (INTRINSIC)WN_intrinsic(tree) == INTRN_I8POPCNT &&
-        Is_Target_64bit() && ( Is_Target_SSE42() || Is_Target_SSE4a() ) ) {
-      // SSE4.2(Intel) and SSE4a(AMD) supports I8 popcnt in 64-bit mode
+        Is_Target_64bit() && ( Is_Target_SSE42() || Is_Target_Barcelona() ) ) {
+      // Support for POPCNT is available with AMD
+      //  Barcelona onwards and Intel Nehalem onwards
       break;
     }
 #endif
Index: osprey/wgen/wgen_expr.cxx
===================================================================
--- osprey/wgen/wgen_expr.cxx	(revision 1439)
+++ osprey/wgen/wgen_expr.cxx	(working copy)
@@ -9249,12 +9249,27 @@
 	        intrinsic_op = TRUE;
 	        break;
                
+#ifdef TARG_X8664
 	      case GSBI_BUILT_IN_POPCOUNT:
+	        iopc = INTRN_I4POPCNT;
+		intrinsic_op = TRUE;
+		break;
 	      case GSBI_BUILT_IN_POPCOUNTL:
+	        iopc = INTRN_I8POPCNT;
+		intrinsic_op = TRUE;
+		break;
 	      case GSBI_BUILT_IN_POPCOUNTLL:
 	        iopc = INTRN_POPCOUNT;
 		intrinsic_op = TRUE;
 		break;
+#else
+	      case GSBI_BUILT_IN_POPCOUNT:
+	      case GSBI_BUILT_IN_POPCOUNTL:
+	      case GSBI_BUILT_IN_POPCOUNTLL:
+	        iopc = INTRN_POPCOUNT;
+		intrinsic_op = TRUE;
+		break;
+#endif
 	
 	      case GSBI_BUILT_IN_PARITY:
 	      case GSBI_BUILT_IN_PARITYL: