Hi, could a gatekeeper please help review the fix for bug941(
https://bugs.open64.net/show_bug.cgi?id=941)?
Thanks to David Coakley to provide the cut-down source code and the
relevant info in the register usage.
below is the info
"
In 32-bit x86 code, %bpl is not a valid register and the compiler
should not generate code that references it. It is one of the 8-bit
registers added in 64-bit mode (see section 3.1.2 in Vol. 1 of the
AMD64 Architecture Programmer's Manual for the complete list).
Attached is a small test case derived from p_driver.c. To reproduce the
problem, execute the following command:
opencc -std=gnu99 -m32 -O2 -c min_bpl.c
"
Analysis:
The bpl (lower 8bit of rbp) is not addressable under 32bit mode. but it is
generated by the EBO post processing phase( after register allocation).
The suggested patch is straightforword. We disable such peephole op changes
in EBO.
--- a/osprey/be/cg/x8664/ebo_special.cxx
+++ b/osprey/be/cg/x8664/ebo_special.cxx
@@ -3507,6 +3507,22 @@ BOOL ICMP_Is_Replaced ( OP *op, TN **opnd_tn,
EBO_TN_INFO **opnd_tninfo )
return FALSE;
}
+ // open64.net bug941. under m32, at ebo post process phase
+ // if the new_top is set to 8bit operator and the GPR is not byte
addressable
+ // we disable the change of op.
+ if ( Is_Target_32bit() &&
+ EBO_in_peep &&
+ ( new_top == TOP_cmpi8 ||
+ new_top == TOP_test8 ||
+ new_top == TOP_testi8 ||
+ new_top == TOP_cmp8)) {
+ const REGISTER_SET regs =
REGISTER_SUBCLASS_members(ISA_REGISTER_SUBCLASS_m32_8bit_regs);
+ if ( TN_is_register(new_src0) && !REGISTER_SET_MemberP(regs,
TN_register(new_src0) ))
+ return FALSE;
+ if ( TN_is_register(new_src1) && !REGISTER_SET_MemberP(regs,
TN_register(new_src1) ))
+ return FALSE;
+ }
+
Could a gatekeeper please help a review? Thanks
Regards
Gang
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