It looks like this branch is redundent?
+ else if (OP_iadd(lda_op))
+ asm_opnd = OP_opnd( lda_op, 1 );
It's fully covered by the else part.
2012/3/16 Gang Yu <yugang...@gmail.com>:
> Hi,
>
> could a gatekeeper please help review the fix for bug955? regression
> caused by r3882.
>
> r3882 causes some regressions on compilation for m32 fpic related
> applications. For example, open64 triple build failed. a cut down bug-case
> below:
>
> opencc -m32 -fpic -S bug955.c
>
> typedef long long mask_t;
> typedef struct phase_struct {
> char key;
> mask_t mask;
> } phase_info_t;
>
> int a[]={3,5};
> static phase_info_t phase_info[] = {
> {'N', 0x0000000000000000LL},
> };
>
>
> typedef enum {
> P_NONE,
> P_All,
> } phases_t;
>
>
> extern mask_t get_phase_mask (phases_t i);
>
> mask_t
> get_phase_mask (phases_t i)
> {
> a[0]=1;
> return phase_info[i].mask;
> }
>
> opencc -m32 -fpic -S bug955.c, we get
> # 20
> # 21 mask_t
> # 22 get_phase_mask (phases_t i)
> # 23 {
> .LBB2_get_phase_mask:
> addl $-12,%esp # [0]
> movl %ebp,4(%esp) # [1] _temp_gra_spill1
> movl %ebx,0(%esp) # [1] _temp_lcl_spill0
> call .LBB3_get_phase_mask # [1] .LBB3_get_phase_mask
> .LBB3_get_phase_mask:
> popl %ebx # [0]
> addl $_GLOBAL_OFFSET_TABLE_+[.-.LBB3_get_phase_mask],%ebx #
> [3]
> .LBB3_get_phase_mask
> .LBB1_get_phase_mask:
> .loc 1 24 0
> # 24 a[0]=1;
> movl a@GOT(%ebx),%ebp # [0] a
> .loc 1 25 0
> # 25 return phase_info[i].mask;
> movl 16(%esp),%eax # [0] i
> .loc 1 24 0
> movl $1,%ecx # [0]
> imull $12,%eax # [3]
> .loc 1 25 0
> movl .data+24(%ebx,%eax,1), %edx # [6] id:8 phase_info+0x0
> movl .data+20(%ebx,%eax,1), %eax # [6] id:8 phase_info+0x0
> .loc 1 24 0
> movl %ecx,0(%ebp) # [7] id:6 a+0x0
> .loc 1 25 0
> movl 0(%esp),%ebx # [7] _temp_lcl_spill0
> movl 4(%esp),%ebp # [7] _temp_gra_spill1
> addl $12,%esp # [8]
> ret # [8]
>
>
> movl .data+24(%ebx,%eax,1), %edx # [6] id:8 phase_info+0x0
> movl .data+20(%ebx,%eax,1), %eax # [6] id:8 phase_info+0x0
> should be
> movl .data@GOTOFF+24(%ebx,%eax,1), %edx
> movl .data@GOTOFF+20(%ebx,%eax,1), %eax
>
> although this is an optimization bug occurs at the EBO phase,
> Compose_Addr_offset ignores the symbol(.data+24) reloc attribute, wrongly
> TN_RELOC_NONE symbol generated. However, we don't want to fix in this way.
> Because TN_RELOC_IA32_GOTOFF is not allowed to be linked in a shared obj to
> external undefined symbols, such info below:
>
> /usr/bin/ld: CMakeFiles/akonadiprivate.dir/shared/akapplication.cpp.o:
> relocation R_386_GOTOFF against undefined symbol `vtable for
> boost::program_options::variables_map' can not be used when making a shared
> object
> Instead, we try to avoid the using of TN_RELOC_IA32_GOTOFF in -fpic code, we
> back to use IA32_GOT as r3881 did. Only in those cases have to change to
> IA32_GOTOFF, we do it.
> the patch:
>
>
> osprey/be/cg/x8664/cgtarget.cxx -- e78cbf9..33ff39a 100644
> --- a/osprey/be/cg/x8664/cgtarget.cxx
> +++ b/osprey/be/cg/x8664/cgtarget.cxx
> @@ -3910,10 +3910,34 @@ TN* CGTARG_Process_Asm_m_constraint( WN* load,
> void** offset, OPS* ops )
> OP* lda_op = OPS_last( ops );
> // open64.net bug951. On finding the symbol TN, don't miss the cases
> of:
> // TN :- ld32 GTN2(%rbx) (sym:base_sym +0)
> - // TN :- lea32 GTN2(%rbx) (sym:base_sym+base_ofst)
> + // and
> + // TN_tmp :- ld32 GTN2(%rbx) (sym:base_sym +0)
> + // TN :- lea32 TN_tmp ofst_TN
> + // result_sym of the first case is
> + // (sym:base_sym + 0), reloc: TN_RELOC_IA32_GOT
> + // result_sym of the latter case is
> + // (sym:base_sym + base_ofst), reloc: TN_RELOC_IA32_GOTOFF
> +
> if (Is_Target_32bit() && Gen_PIC_Shared) {
> - asm_opnd = OP_iadd(lda_op) ? OP_opnd( lda_op, 1 ) :
> - (OP_code(lda_op) == TOP_ldc32) ? OP_opnd( lda_op, 0) : OP_opnd(
> lda_op, 1);
> + OP * prev_lda = OP_prev(lda_op);
> + if (OP_code(lda_op) == TOP_lea32 &&
> + prev_lda &&
> + OP_code(prev_lda) == TOP_ld32 &&
> + TN_is_constant(OP_opnd(lda_op, 1)) &&
> + TN_register(OP_opnd(lda_op, 0)) ==
> TN_register(OP_result(prev_lda, 0)) &&
> + TN_is_symbol(OP_opnd(prev_lda, 1)) &&
> + TN_relocs(OP_opnd(prev_lda, 1)) == TN_RELOC_IA32_GOT) {
> + asm_opnd = Gen_Symbol_TN( TN_var(OP_opnd(prev_lda, 1)),
> + TN_value(OP_opnd(lda_op, 1)),
> + TN_RELOC_IA32_GOTOFF );
> + OPS_Remove_Op (ops, prev_lda);
> + }
> + else if (OP_iadd(lda_op))
> + asm_opnd = OP_opnd( lda_op, 1 );
> + else if (OP_code(lda_op) == TOP_ldc32)
> + asm_opnd = OP_opnd( lda_op, 0);
> + else
> + asm_opnd = OP_opnd( lda_op, 1 );
> } else {
> asm_opnd = OP_iadd(lda_op) ? OP_opnd( lda_op, 1 ) : OP_opnd( lda_op,
> 0 );
> }
> osprey/be/cg/x8664/exp_loadstore.cxx -- 58cb61e..81158d5 100644
> --- a/osprey/be/cg/x8664/exp_loadstore.cxx
> +++ b/osprey/be/cg/x8664/exp_loadstore.cxx
> @@ -1267,29 +1267,18 @@ Exp_Ldst (
> STB_section(base_sym) /* bug 10097 */)) ){
> FmtAssert(!ST_is_thread_local(base_sym),
> ("Exp_Ldst: thread-local storage NYI under PIC"));
> + TN* tmp = base_ofst == 0 ? tn : Build_TN_Like(tn);
> + Build_OP( TOP_ld32, tmp, Ebx_TN(),
> + Gen_Symbol_TN( base_sym, 0, TN_RELOC_IA32_GOT ),
> + &newops );
> - // open64.net bug951.
> - // when base_ofst ! = 0, we generate
> - // TN :- lea32 GTN2(%rbx) (sym:base_sym+base_ofst)
> - // instead of
> - // tmp_TN :- ld32 GT2(%bx) (sym:base_sym + 0)
> - // TN :- lea32 tmp_TN base_ofst
> - // this is for consideration of facilitate restoring the register
> TN
> - // to symbol TN in ASM m constraint.
> - // And also this reduces a temp TN.
> -
> - if (base_ofst == 0)
> - Build_OP( TOP_ld32, tn, Ebx_TN(),
> - Gen_Symbol_TN( base_sym, base_ofst, TN_RELOC_IA32_GOT
> ),
> - &newops );
> - else
> - Build_OP( TOP_lea32, tn, Ebx_TN(),
> - Gen_Symbol_TN( base_sym, base_ofst,
> TN_RELOC_IA32_GOTOFF ),
> - &newops );
> // got address should not alias
> Set_OP_no_alias(OPS_last(&newops));
> PU_References_GOT = TRUE;
> + if( base_ofst != 0 ){
> + Build_OP( TOP_lea32, tn, tmp, Gen_Literal_TN(base_ofst, 4),
> &newops );
> + }
> } else {
> Build_OP( TOP_ldc32, tn,
> Gen_Symbol_TN( base_sym, base_ofst, TN_RELOC_NONE ),
> TIA for review
>
> Regards
> Gang
>
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--
Regards,
Lai Jian-Xin
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