From: "Nicolas J. Bouliane" <[email protected]>

Signed-off-by: Nicolas J. Bouliane <[email protected]>
---
 src/osmo-bts-sysmo/l1_if.c        |    1 +
 src/osmo-bts-sysmo/l1_if.h        |    1 +
 src/osmo-bts-sysmo/main.c         |   24 ++++++++++++++++++++++++
 src/osmo-bts-sysmo/sysmobts_vty.c |   21 ++++++++++++++++++++-
 4 files changed, 46 insertions(+), 1 deletion(-)

diff --git a/src/osmo-bts-sysmo/l1_if.c b/src/osmo-bts-sysmo/l1_if.c
index 16f1523..e16bb49 100644
--- a/src/osmo-bts-sysmo/l1_if.c
+++ b/src/osmo-bts-sysmo/l1_if.c
@@ -1267,6 +1267,7 @@ struct femtol1_hdl *l1if_open(void *priv)
 
        fl1h->priv = priv;
        fl1h->clk_cal = 0;
+       fl1h->clk_use_eeprom = 1;
        fl1h->ul_power_target = -75;    /* dBm default */
        fl1h->min_qual_rach = MIN_QUAL_RACH;
        fl1h->min_qual_norm = MIN_QUAL_NORM;
diff --git a/src/osmo-bts-sysmo/l1_if.h b/src/osmo-bts-sysmo/l1_if.h
index 7947ea2..cf8af7b 100644
--- a/src/osmo-bts-sysmo/l1_if.h
+++ b/src/osmo-bts-sysmo/l1_if.h
@@ -42,6 +42,7 @@ struct femtol1_hdl {
        struct gsm_time gsm_time;
        uint32_t hLayer1;                       /* handle to the L1 instance in 
the DSP */
        uint32_t dsp_trace_f;
+       uint8_t clk_use_eeprom;
        int clk_cal;
        int ul_power_target;
        uint8_t clk_src;
diff --git a/src/osmo-bts-sysmo/main.c b/src/osmo-bts-sysmo/main.c
index 595a6eb..d535ac8 100644
--- a/src/osmo-bts-sysmo/main.c
+++ b/src/osmo-bts-sysmo/main.c
@@ -48,6 +48,7 @@
 
 #define SYSMOBTS_RF_LOCK_PATH  "/var/lock/bts_rf_lock"
 
+#include "eeprom.h"
 #include "l1_if.h"
 
 /* FIXME: read from real hardware */
@@ -80,6 +81,27 @@ int bts_model_init(struct gsm_bts *bts)
        return 0;
 }
 
+/* Set the clock calibration to the value
+ * read from the eeprom.
+ */
+void clk_cal_use_eeprom(struct gsm_bts *bts)
+{
+       int rc;
+       struct femtol1_hdl *hdl;
+       eeprom_RfClockCal_t rf_clk;
+
+       hdl = bts->c0->role_bts.l1h;
+
+       if (!hdl || !hdl->clk_use_eeprom)
+               return;
+
+       rc = eeprom_ReadRfClockCal(&rf_clk);
+       if (rc != EEPROM_SUCCESS)
+               return;
+       else
+               hdl->clk_cal = rf_clk.iClkCor;
+}
+
 struct ipabis_link *link_init(struct gsm_bts *bts, const char *ip)
 {
        struct ipabis_link *link = talloc_zero(bts, struct ipabis_link);
@@ -286,6 +308,8 @@ int main(int argc, char **argv)
                exit(1);
        }
 
+       clk_cal_use_eeprom(bts);
+
        if (stat(SYSMOBTS_RF_LOCK_PATH, &st) == 0) {
                LOGP(DL1C, LOGL_NOTICE, "Not starting BTS due to RF_LOCK file 
present\n");
                exit(23);
diff --git a/src/osmo-bts-sysmo/sysmobts_vty.c 
b/src/osmo-bts-sysmo/sysmobts_vty.c
index 5bc948e..21b7f89 100644
--- a/src/osmo-bts-sysmo/sysmobts_vty.c
+++ b/src/osmo-bts-sysmo/sysmobts_vty.c
@@ -111,6 +111,18 @@ DEFUN(cfg_trx_no_gsmtap_sapi, cfg_trx_no_gsmtap_sapi_cmd,
        return CMD_SUCCESS;
 }
 
+DEFUN(cfg_trx_clkcal_eeprom, cfg_trx_clkcal_eeprom_cmd,
+       "clock-calibration eeprom",
+       "Use the eeprom clock calibration value\n")
+{
+       struct gsm_bts_trx *trx = vty->index;
+       struct femtol1_hdl *fl1h = trx_femtol1_hdl(trx);
+
+       fl1h->clk_use_eeprom = 1;
+
+       return CMD_SUCCESS;
+}
+
 DEFUN(cfg_trx_clkcal_def, cfg_trx_clkcal_def_cmd,
        "clock-calibration default",
        "Set the clock calibration value\n" "Default Clock DAC value\n")
@@ -118,6 +130,7 @@ DEFUN(cfg_trx_clkcal_def, cfg_trx_clkcal_def_cmd,
        struct gsm_bts_trx *trx = vty->index;
        struct femtol1_hdl *fl1h = trx_femtol1_hdl(trx);
 
+       fl1h->clk_use_eeprom = 0;
        fl1h->clk_cal = 0xffff;
 
        return CMD_SUCCESS;
@@ -132,6 +145,7 @@ DEFUN(cfg_trx_clkcal, cfg_trx_clkcal_cmd,
        struct gsm_bts_trx *trx = vty->index;
        struct femtol1_hdl *fl1h = trx_femtol1_hdl(trx);
 
+       fl1h->clk_use_eeprom = 0;
        fl1h->clk_cal = clkcal & 0xfff;
 
        return CMD_SUCCESS;
@@ -145,6 +159,7 @@ DEFUN(cfg_trx_clkcal, cfg_trx_clkcal_cmd,
        struct gsm_bts_trx *trx = vty->index;
        struct femtol1_hdl *fl1h = trx_femtol1_hdl(trx);
 
+       fl1h->clk_use_eeprom = 0;
        fl1h->clk_cal = clkcal;
 
        return CMD_SUCCESS;
@@ -476,7 +491,10 @@ void bts_model_config_write_trx(struct vty *vty, struct 
gsm_bts_trx *trx)
        struct femtol1_hdl *fl1h = trx_femtol1_hdl(trx);
        int i;
 
-       vty_out(vty, "  clock-calibration %d%s", fl1h->clk_cal,
+       if (fl1h->clk_use_eeprom)
+               vty_out(vty, "  clock-calibration eeprom%s", VTY_NEWLINE);
+       else
+               vty_out(vty, "  clock-calibration %d%s", fl1h->clk_cal,
                        VTY_NEWLINE);
        if (fl1h->calib_path)
                vty_out(vty, "  trx-calibration-path %s%s",
@@ -549,6 +567,7 @@ int bts_model_vty_init(struct gsm_bts *bts)
        install_element(BTS_NODE, &cfg_bts_no_auto_band_cmd);
 
        install_element(TRX_NODE, &cfg_trx_clkcal_cmd);
+       install_element(TRX_NODE, &cfg_trx_clkcal_eeprom_cmd);
        install_element(TRX_NODE, &cfg_trx_clkcal_def_cmd);
        install_element(TRX_NODE, &cfg_trx_clksrc_cmd);
        install_element(TRX_NODE, &cfg_trx_cal_path_cmd);
-- 
1.7.10.4


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