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- Log -----------------------------------------------------------------
commit 819df1aa78e186cdddef066ff51858fa85776dc0
Author: James Simmons <jsimm...@infradead.org>
Date: Sun Nov 4 20:39:15 2012 -0500
Fixed the PLL code. The first problem was only IGA1 PLL was being
programmed completely in via_set_vclk. Fixed up the code also to actually
program the IGA2 PLL. The other huge change was the move from PLL MNR tables to
instead generating the program register values on the fly from the mode clock.
This greatly improves the quality of the image on the display. Also as a bonus
CLE266 works with various modes were as before it was broken for several modes.
The function via_get_clk_value is now formated that it can also create the
values for ECLK as well as the HDMI pixel clock since the registers are layed
out in the same format.
-----------------------------------------------------------------------
Summary of changes:
drivers/gpu/drm/via/via_clocks.c | 576 +++++++++++--------------------------
drivers/gpu/drm/via/via_crtc.c | 6 +-
drivers/gpu/drm/via/via_display.h | 3 +-
drivers/gpu/drm/via/via_pll.h | 533 ----------------------------------
4 files changed, 173 insertions(+), 945 deletions(-)
delete mode 100644 drivers/gpu/drm/via/via_pll.h
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DRM driver for VIA IGPs
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