drivers/gpu/drm/via/Makefile | 2
drivers/gpu/drm/via/via_crtc.c | 44 +++++++++++++++++++
drivers/gpu/drm/via/via_display.c | 10 ++++
drivers/gpu/drm/via/via_display.h | 6 ++
drivers/gpu/drm/via/via_drv.c | 5 ++
drivers/gpu/drm/via/via_drv.h | 5 ++
drivers/gpu/drm/via/via_regs.h | 87 ++++++++++++++++++++++++++++++++++++++
7 files changed, 158 insertions(+), 1 deletion(-)
New commits:
commit 5822fd0e8f080c28e87075d61b5e963ca0d32198
Author: James Simmons <jsimm...@infradead.org>
Date: Sun Mar 24 16:18:20 2013 -0400
The rest of the changes needed to make HDMI work properly
diff --git a/drivers/gpu/drm/via/Makefile b/drivers/gpu/drm/via/Makefile
index 136014b..62f4fc7 100644
--- a/drivers/gpu/drm/via/Makefile
+++ b/drivers/gpu/drm/via/Makefile
@@ -7,6 +7,6 @@ via-y := via_drv.o via_pm.o via_i2c.o via_irq.o
via_verifier.o via_ioc32.o \
init_ttm.o ttm_gem.o via_ttm.o via_fence.o via_sgdma.o \
via_h1_dma.o via_h1_cmdbuf.o via_video.o \
via_display.o via_crtc.o via_fb.o crtc_hw.o via_clocks.o \
- via_analog.o via_lvds.o
+ via_analog.o via_lvds.o via_hdmi.o
obj-$(CONFIG_DRM_VIA) += via.o
diff --git a/drivers/gpu/drm/via/via_crtc.c b/drivers/gpu/drm/via/via_crtc.c
index df15b9e..3933e00 100644
--- a/drivers/gpu/drm/via/via_crtc.c
+++ b/drivers/gpu/drm/via/via_crtc.c
@@ -385,6 +385,50 @@ via_load_fifo_regs(struct via_crtc *iga, struct
drm_display_mode *mode)
load_value_to_registers(VGABASE, &iga->display_queue, reg_value);
}
+/* Load CRTC Pixel Timing registers */
+void via_load_crtc_pixel_timing(struct drm_crtc *crtc, struct drm_display_mode
*mode)
+{
+ struct via_crtc *iga = container_of(crtc, struct via_crtc, base);
+ struct drm_via_private *dev_priv = crtc->dev->dev_private;
+ u32 reg_value = 0;
+
+ reg_value = IGA1_PIXELTIMING_HOR_TOTAL_FORMULA(mode->crtc_htotal);
+ load_value_to_registers(VGABASE, &iga->pixel_timings.htotal, reg_value);
+
+ reg_value = IGA1_PIXELTIMING_HOR_ADDR_FORMULA(mode->crtc_hdisplay);
+ load_value_to_registers(VGABASE, &iga->pixel_timings.hdisplay,
reg_value);
+
+ reg_value =
IGA1_PIXELTIMING_HOR_BLANK_START_FORMULA(mode->crtc_hblank_start);
+ load_value_to_registers(VGABASE, &iga->pixel_timings.hblank_start,
reg_value);
+
+ reg_value =
IGA1_PIXELTIMING_HOR_BLANK_END_FORMULA(mode->crtc_hblank_end);
+ load_value_to_registers(VGABASE, &iga->pixel_timings.hblank_end,
reg_value);
+
+ reg_value =
IGA1_PIXELTIMING_HOR_SYNC_START_FORMULA(mode->crtc_hsync_start);
+ load_value_to_registers(VGABASE, &iga->pixel_timings.hsync_start,
reg_value);
+
+ reg_value = IGA1_PIXELTIMING_HOR_SYNC_END_FORMULA(mode->crtc_hsync_end);
+ load_value_to_registers(VGABASE, &iga->pixel_timings.hsync_end,
reg_value);
+
+ reg_value = IGA1_PIXELTIMING_VER_TOTAL_FORMULA(mode->crtc_vtotal);
+ load_value_to_registers(VGABASE, &iga->pixel_timings.vtotal, reg_value);
+
+ reg_value = IGA1_PIXELTIMING_VER_ADDR_FORMULA(mode->crtc_vdisplay);
+ load_value_to_registers(VGABASE, &iga->pixel_timings.vdisplay,
reg_value);
+
+ reg_value =
IGA1_PIXELTIMING_VER_BLANK_START_FORMULA(mode->crtc_vblank_start);
+ load_value_to_registers(VGABASE, &iga->pixel_timings.vblank_start,
reg_value);
+
+ reg_value =
IGA1_PIXELTIMING_VER_BLANK_END_FORMULA(mode->crtc_vblank_end);
+ load_value_to_registers(VGABASE, &iga->pixel_timings.vblank_end,
reg_value);
+
+ reg_value =
IGA1_PIXELTIMING_VER_SYNC_START_FORMULA(mode->crtc_vsync_start);
+ load_value_to_registers(VGABASE, &iga->pixel_timings.vsync_start,
reg_value);
+
+ reg_value = IGA1_PIXELTIMING_VER_SYNC_END_FORMULA(mode->crtc_vsync_end);
+ load_value_to_registers(VGABASE, &iga->pixel_timings.vsync_end,
reg_value);
+}
+
/* Load CRTC timing registers */
void via_load_crtc_timing(struct via_crtc *iga, struct drm_display_mode *mode)
{
diff --git a/drivers/gpu/drm/via/via_display.c
b/drivers/gpu/drm/via/via_display.c
index 331fa2c..9f9cda8 100644
--- a/drivers/gpu/drm/via/via_display.c
+++ b/drivers/gpu/drm/via/via_display.c
@@ -137,6 +137,7 @@ via_encoder_commit(struct drm_encoder *encoder)
default:
DRM_ERROR("Unsupported DIPort.\n");
+ case DISP_DI_NONE:
break;
}
@@ -200,6 +201,7 @@ via_encoder_disable(struct drm_encoder *encoder)
default:
DRM_ERROR("Unsupported DIPort.\n");
+ case DISP_DI_NONE:
break;
}
}
@@ -246,6 +248,7 @@ via_set_sync_polarity(struct drm_encoder *encoder, struct
drm_display_mode *mode
default:
DRM_ERROR("No DIPort.\n");
+ case DISP_DI_NONE:
break;
}
}
@@ -483,6 +486,13 @@ via_modeset_init(struct drm_device *dev)
via_lvds_init(dev);
+ if ((dev->pdev->device != PCI_DEVICE_ID_VIA_CLE266) ||
+ (dev->pdev->device != PCI_DEVICE_ID_VIA_KM400) ||
+ (dev->pdev->device != PCI_DEVICE_ID_VIA_K8M800) ||
+ (dev->pdev->device != PCI_DEVICE_ID_VIA_PM800) ||
+ (dev->pdev->device != PCI_DEVICE_ID_VIA_CN700))
+ via_hdmi_init(dev, DISP_DI_NONE);
+
/*
* Set up the framebuffer device
*/
diff --git a/drivers/gpu/drm/via/via_display.h
b/drivers/gpu/drm/via/via_display.h
index 6a54548..148f69a 100644
--- a/drivers/gpu/drm/via/via_display.h
+++ b/drivers/gpu/drm/via/via_display.h
@@ -26,6 +26,7 @@
#include <video/vga.h>
#include "crtc_hw.h"
+#include "drm_edid.h"
#include "drm_crtc.h"
#include "drm_crtc_helper.h"
#include "drm_fb_helper.h"
@@ -54,6 +55,7 @@
struct via_crtc {
struct drm_crtc base;
struct ttm_bo_kmap_obj cursor_kmap;
+ struct crtc_timings pixel_timings;
struct crtc_timings timings;
unsigned int display_queue_expire_num;
unsigned int fifo_high_threshold;
@@ -72,6 +74,7 @@ struct via_crtc {
struct via_connector {
struct drm_connector base;
struct i2c_adapter *ddc_bus;
+ uint32_t flags;
};
#define DISP_DI_NONE 0x00
@@ -136,6 +139,8 @@ extern int via_framebuffer_init(struct drm_device *dev,
struct drm_fb_helper **p
extern void via_framebuffer_fini(struct drm_device *dev);
/* crtc */
+extern void via_load_crtc_pixel_timing(struct drm_crtc *crtc,
+ struct drm_display_mode *mode);
extern void via_crtc_init(struct drm_device *dev, int index);
/* encoders */
@@ -151,6 +156,7 @@ extern void via_encoder_commit(struct drm_encoder *encoder);
extern void via_connector_destroy(struct drm_connector *connector);
extern int via_get_edid_modes(struct drm_connector *connector);
+extern void via_hdmi_init(struct drm_device *dev, int diPort);
extern void via_analog_init(struct drm_device *dev);
extern void via_lvds_init(struct drm_device *dev);
diff --git a/drivers/gpu/drm/via/via_drv.c b/drivers/gpu/drm/via/via_drv.c
index c0d100c..68b38b4 100644
--- a/drivers/gpu/drm/via/via_drv.c
+++ b/drivers/gpu/drm/via/via_drv.c
@@ -34,6 +34,11 @@ int via_modeset = 0;
MODULE_PARM_DESC(modeset, "Disable/Enable modesetting");
module_param_named(modeset, via_modeset, int, 0400);
+int via_hdmi_audio = 0;
+
+MODULE_PARM_DESC(audio, "HDMI Audio enable (1 = enable)");
+module_param_named(audio, via_hdmi_audio, int, 0444);
+
static struct pci_device_id via_pci_table[] = {
viadrv_PCI_IDS,
};
diff --git a/drivers/gpu/drm/via/via_drv.h b/drivers/gpu/drm/via/via_drv.h
index 70bc2ee..1d3b86de 100644
--- a/drivers/gpu/drm/via/via_drv.h
+++ b/drivers/gpu/drm/via/via_drv.h
@@ -175,11 +175,16 @@ struct drm_via_private {
#define VIA_READ8(reg) ioread8(VIA_BASE + reg)
#define VIA_WRITE8(reg, val) iowrite8(val, VIA_BASE + reg)
+#define VIA_WRITE_MASK(reg, data, mask) \
+ VIA_WRITE(reg, (data & mask) | (VIA_READ(reg) & ~mask)) \
+
#define VGABASE (VIA_BASE+VIA_MMIO_VGABASE)
extern struct drm_ioctl_desc via_ioctls[];
extern int via_max_ioctl;
+extern int via_hdmi_audio;
+
extern void via_engine_init(struct drm_device *dev);
extern int via_dma_init(struct drm_device *dev, void *data, struct drm_file
*file_priv);
diff --git a/drivers/gpu/drm/via/via_regs.h b/drivers/gpu/drm/via/via_regs.h
index 7dc93c9..ae74eb7 100644
--- a/drivers/gpu/drm/via/via_regs.h
+++ b/drivers/gpu/drm/via/via_regs.h
@@ -207,4 +207,91 @@
/* CN400 HQV offset */
#define REG_HQV1_INDEX 0x00001000
+/************************************************
+ * DisplayPort Register
+ ************************************************/
+#define DP_DATA_PASS_ENABLE_REG 0xC000
+
+#define DP_ATTR_DATA_REG 0xC610
+#define DP_LINK_TRAINING_REG 0xC614
+#define DP_VIDEO_CTRL_REG 0xC618
+#define DP_VER_EXT_PKT_HEAD_REG 0xC61C
+
+/* DP Display Port Enable and InfoFrame Control */
+#define DP_ENABLE_IF_REG 0xC640
+#define DP_HWIDTH_TUSIZE_REG 0xC644
+#define DP_HLINE_DUR_REG 0xC648
+#define DP_MVID_MISC0_REG 0xC64C
+
+#define DP_H_ATTR_REG 0xC650
+#define DP_HV_START_REG 0xC654
+#define DP_POLARITY_WIDTH_REG 0xC658
+#define DP_ACITVE_WH_REG 0xC65C
+
+#define AUX_W_DATA0_REG 0xC710
+#define AUX_W_DATA1_REG 0xC714
+#define AUX_W_DATA2_REG 0xC718
+#define AUX_W_DATA3_REG 0xC71C
+
+#define AUX_R_DATA0_REG 0xC720
+#define AUX_R_DATA1_REG 0xC724
+#define AUX_R_DATA2_REG 0xC728
+#define AUX_R_DATA3_REG 0xC72C
+#define VIA_IRQ_DP_HOT_IRQ 0xC0000000
+#define VIA_IRQ_DP_HOT_UNPLUG 0x80000000
+#define VIA_IRQ_DP_HOT_PLUG 0x40000000
+#define VIA_IRQ_DP_NO_INT 0x00000000
+
+#define AUX_TIMER_REG 0xC730
+#define AUX_CMD_REG 0xC734
+#define DP_NAUD_MUTE_REG 0xC738
+
+#define DP_EPHY_PLL_REG 0xC740
+#define DP_EPHY_TX_PWR_REG 0xC744
+#define DP_EPHY_MISC_PWR_REG 0xC748
+
+/*************************************************
+ * DisplayPort2 Register
+ *************************************************/
+#define DP2_NVID_MISC0_REG 0xC690
+#define DP2_LINK_TRAINING_REG 0xC694
+#define DP2_VIDEO_CTRL_REG 0xC698
+#define DP2_EXT_REG 0xC69C
+#define DP2_VER_EXT_PKT_HEAD_REG 0xC61C
+
+/* DP2 Display Port Enable and InfoFrame Control */
+#define DP2_ENABLE_IF_REG 0xC6C0
+#define DP2_HWIDTH_TUSIZE_REG 0xC6C4
+#define DP2_HLINE_DUR_REG 0xC6C8
+#define DP2_MVID_MISC0_REG 0xC6CC
+
+#define DP2_H_ATTR_REG 0xC6D0
+#define DP2_HV_START_REG 0xC6D4
+#define DP2_POLARITY_WIDTH_REG 0xC6D8
+#define DP2_ACITVE_WH_REG 0xC6DC
+
+/* the same with DP1 */
+#define DP2_EPHY_SSC_REG 0xC740
+/* the same with DP1 */
+#define DP2_EPHY_RT_REG 0xC744
+
+#define DP2_AUX_W_DATA0_REG 0xC790
+#define DP2_AUX_W_DATA1_REG 0xC794
+#define DP2_AUX_W_DATA2_REG 0xC798
+#define DP2_AUX_W_DATA3_REG 0xC79C
+
+#define DP2_AUX_R_DATA0_REG 0xC7A0
+#define DP2_AUX_R_DATA1_REG 0xC7A4
+#define DP2_AUX_R_DATA2_REG 0xC7A8
+#define DP2_AUX_R_DATA3_REG 0xC7AC
+
+#define DP2_AUX_TIMER_REG 0xC7B0
+#define DP2_AUX_CMD_REG 0xC7B4
+#define DP2_NAUD_MUTE_REG 0xC7B8
+
+#define DP2_EPHY_TX_PWR_REG2 0xC7C0
+#define DP2_EPHY_TX_IDLE_REG 0xC7C4
+#define DP2_EPHY_TX_PWR_REG 0xC7C8
+#define DP2_EPHY_PLL_REG 0xC7CC
+
#endif /* _VIA_REGS_H_ */
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